Job Title: Senior ASIC/SoC RTL Engineer/Lead
Location: Wipro
Experience Required: 9 - 20 years
Responsibilities:
- Design and integration of IP, Subsystem/Cluster, and SoC level using Verilog/SystemVerilog
- Perform RTL quality checks (Lint, CDC)
- Assist in synthesis and low power design considerations
- Understand and implement AMBA bus protocols (AXI, AHB, ATB, APB)
- Apply timing analysis and constraints
- Interface with protocols like DDR, Ethernet, I2C, UART, SPI
- Set up and use tools such as Spyglass Lint/CDC and Synopsys Design Compiler (DC)
- Develop and utilize scripting in Make, Perl, Shell, Python
- Collaborate with physical design, verification, DFT, and software teams
- Review and create design documentation for multiple subsystems
- Debug and resolve issues across subsystems
Qualifications:
- Expertise in IP design, subsystem integration, and verification
- Knowledge of RTL quality checks and protocols
- Familiarity with scripting and processor architecture (ARM) is a plus
About Wipro:
Wipro Limited is a leading technology services and consulting company focused on digital transformation. With nearly 245,000 employees across 65 countries, Wipro helps clients build innovative, sustainable businesses. We are an Equal Employment Opportunity employer.
Additional Information:
- Seniority Level: Mid-Senior level
- Employment Type: Full-time
- Job Function: Design, Engineering, IT
- Industries: IT Services and Consulting