ASIC RTL Design Engineer

Weekday 1; Hyderabad; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Weekday 1 in Hyderabad is seeking experienced ASIC RTL Design professionals to join our semiconductor engineering team from Senior Engineer to Architect levels. You will contribute to architecture, development and block-level RTL for complex ASIC products.

You will translate architectural specs into synthesizable RTL, collaborate with verification and physical design teams, and mentor juniors where appropriate.

Qualifications

• 6+ years of hands-on ASIC RTL design or digital hardware development.
• Strong grounding in digital design fundamentals, RTL coding, and ASIC design methodologies.
• Proven experience developing synthesizable RTL for complex digital systems.
• Proficiency in Verilog/SystemVerilog and RTL design practices.

Responsibilities

• Develop high-quality, synthesizable RTL designs based on architectural and microarchitectural specs.
• Translate system requirements into efficient digital hardware implementations.
• Design and implement complex digital logic blocks for ASIC products.
• Participate in microarchitecture definition, design reviews, and technical discussions.
• Develop clean, reusable RTL using industry-standard design methodologies.
• Collaborate with verification teams to define design requirements and resolve issues.
• Debug RTL and simulations, and work with verification to identify root causes.
• Support synthesis, timing analysis, linting, CDC, and other design-quality activities.
• Analyze and optimize designs for power, performance, and area (PPA).
• Work with physical design teams to address constraints and integration challenges.
• Review specifications, RTL, and documentation for quality and completeness.
• Contribute to improving RTL design methodologies and coding standards.
• Senior/Architect roles: provide technical leadership, mentor engineers, drive complex initiatives.

Skills

RTL Design

Verilog/SystemVerilog

ASIC Development

Digital Logic

Synthesis

PPA Trade-offs

Job description

This role is for one of the Weekday's clients

Salary range: Rs 3000000 - Rs 5000000 (ie INR 30-50 LPA)

Experience: 6+ yrs

Location: Hyderabad, Telangana, India

Job Type: Full-time

We are looking for experiencedASIC RTL Design professionalsto join the semiconductor engineering team at Senior Engineer through Architect levels. This role is suited for highly skilled engineers who have strong expertise in RTL design, digital logic, and ASIC development and are looking to contribute to the architecture and implementation of complex semiconductor products.

You will be involved across key stages of the RTL design lifecycle, from understanding architectural specifications and developing microarchitecture to writing synthesizable RTL, supporting verification, and resolving design issues. Depending on your experience level, you may also take ownership of design blocks, provide technical leadership, and contribute to architectural decisions.

Requirements

Key Responsibilities

• Develop high-quality, synthesizableRTL designsbased on architectural and microarchitectural specifications.


• Translate system requirements into efficient digital hardware implementations.


• Design and implement complex digital logic blocks for ASIC products.


• Participate in microarchitecture definition, design reviews, and technical discussions.


• Develop clean, reusable, and scalable RTL using industry-standard design methodologies.


• Collaborate with verification teams to define design requirements and resolve functional issues.


• Debug RTL and simulation issues and work closely with verification teams to identify root causes.


• Support synthesis, timing analysis, linting, CDC, and other design-quality activities.


• Analyze and optimize designs forperformance, power, area, and reliability.


• Work closely with physical design and implementation teams to address design constraints and integration challenges.


• Review specifications, RTL, design documentation, and technical deliverables for quality and completeness.


• Contribute to improving RTL design methodologies, coding standards, and development processes.


• For senior and architect-level roles, provide technical leadership, mentor engineers, and drive complex design initiatives.


• Participate in cross-functional technical reviews and contribute to architectural decisions.

What Makes You a Great Fit

• 6+ years of hands‑on experiencein ASIC RTL design or digital hardware development.


• Strong understanding ofdigital design fundamentals, RTL coding, and ASIC design methodologies.


• Proven experience developing synthesizable RTL for complex digital systems.


• Strong proficiency inVerilog/SystemVerilogand RTL design practices.


• Experience with simulation, debugging, linting, CDC, synthesis, and other RTL design‑quality processes.


• Good understanding of ASIC development flows and collaboration across design, verification, and physical design teams.


• Ability to analyze complex technical problems and develop efficient, reliable solutions.


• Strong understanding of design trade‑offs involvingpower, performance, and area (PPA).


• Excellent problem‑solving, communication, and technical documentation skills.


• Ability to work independently while collaborating effectively with cross‑functional engineering teams.


• Senior Engineer candidates should demonstrate ownership of complex RTL blocks, while Architect‑level candidates should have strong experience inmicroarchitecture, technical leadership, and design strategy.


• A strong passion for semiconductor technology and the ability to continuously learn and adapt to evolving ASIC design methodologies.