Principal ASIC Design Engineer

MaxLinear; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

MaxLinear in Bengaluru seeks a Principal ASIC Design Engineer to lead architecture, micro-architecture, and RTL design of high-performance packet processing and system control blocks in a multi-CPU SoC environment.

You will collaborate across disciplines, apply industry-standard verification methodologies, and drive power-efficient digital designs with a focus on learning, innovation, and engineering excellence.

Qualifications

• BE/M.Tech in Electronics Engineering.
• 15+ years of experience in Digital ASIC implementation at subsystem level or chip level.
• Experience with RTL design using Verilog, SystemVerilog or VHDL.
• Expertise in translation of requirements to ASIC solutions meeting PPA.
• Strong digital logic and CMOS fundamentals; knowledge of ASIC methodologies.
• Experience with scripting languages to automate tasks.
• Knowledge of packet processing, networking fundamentals, or SOC systems.
• Proficiency in SV/UVM-based verification.
• Ability to communicate clearly in writing and speech.
• Experience with design and verification tools.

Responsibilities

• Lead architecture, micro-architecture, and RTL design for high-performance packet processing.
• Integrate logic blocks with embedded processors in multi-CPU SoCs.
• Apply industry-standard design and verification methodologies.
• Collaborate with cross-domain teams to solve complex problems.
• Mentor junior engineers and drive design quality.

Skills

RTL design

Verilog/SystemVerilog/VHDL

Digital ASIC design

Packet processing architectures

SoC/CPU architecture

CMOS technology

Debugging/problem solving

Cross-functional collaboration

Scripting (Python, C)

Education

BE/M.Tech in Electronics Engineering

Tools

UVM

Python

C

STA Tools

Job description

Responsibilities

MaxLinear is seeking a Principal ASIC Design Engineer to join our Digital ASIC Design group. The Digital ASIC team delivers innovative and scalable ASIC solutions addressing complex challenges in the optical and wireless communications domain. In this senior technical role, you will lead the architecture, micro-architecture, and RTL design of high-performance packet processing, interface, and system control blocks. You will also be responsible for the integration of these logic components along with custom or 3 rd party embedded processors in multi-CPU SoC environments, contributing to highly integrated and power‑efficient designs. This position requires expertise in packet processing architectures, understanding of computer networking fundamentals, strong grounding in digital design and CMOS logic, and experience applying industry‑standard design and verification methodologies. Proficiency with modern design and verification tools is essential. Experience with low‑power design techniques is highly desirable. The ideal candidate is a curious, highly motivated engineer with a relentless drive to learn, innovate, and solve complex problems. You bring a “never give up” attitude and thrive when tackling technically demanding challenges. You value collaboration across disciplines and leverage the differences in skill sets with cross‑domain teams to contribute to collective problem‑solving. You aspire to make a lasting technical impact while continuously raising the bar for design quality and engineering excellence.

Qualifications

• BE/M.Tech in Electronics Engineering
• 15+ years of experience in Digital ASIC implementation at subsystem level or chip level including RTL design skills using Verilog, System Verilog or VHDL
• Strong analytical and problem‑solving skills
• Proved expertise in translating engineering requirements to working ASIC solutions meeting PPA
• Strong fundamentals and proven expertise in digital logic design, CMOS technology and ASIC design methodology
• Strong fundamentals in basic circuit design, device physics
• Strong fundamentals in programming, CPU architecture and SOC systems
• Specialization in Communication systems, Networking, or Processor systems
• Passion for learning and engineering great solutions
• Block level verification using SV, UVM, Python or C using industry standard tools
• Basic knowledge and ability to synthesize and perform STA with industry standard tools either for ASIC or FPGA
• Proven written and verbal communication skills that demonstrate clarity of thought and conviction
• Working knowledge of one or more scripting languages and ability to use them to automate/accelerate design and analysis tasks