Senior / Lead / Principal RTL Design Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru seeks an experienced Senior/Lead/Principal RTL Design Engineer to drive microarchitecture to RTL implementation, verification, synthesis and sign‑off for complex designs.

You will own IP/SoC blocks, collaborate with Architecture, Verification and Physical Design teams, optimize PPA, and mentor engineers while shaping RTL coding standards.

Qualifications

• 7–20+ years of experience in RTL/ Digital Design required.
• Hands-on experience with Verilog and SystemVerilog.
• Strong understanding of microarchitecture and digital logic design.

Responsibilities

• Understand and contribute to microarchitecture specifications and design requirements.
• Design and implement complex IP, subsystem, SoC, CPU/ GPU or processor blocks.
• Participate in microarchitecture definition, design reviews and RTL architecture discussions.
• Develop optimized RTL considering performance, power and area (PPA).
• Work closely with Architecture, Verification, Physical Design and STA teams.
• Perform RTL simulation, debugging and functional issue resolution.
• Support lint, CDC, synthesis, STA and other design-quality checks.
• Analyze and resolve timing, area, power and functional issues.
• Drive design closure and support integration of RTL blocks into larger SoC designs.
• Mentor junior engineers and contribute to RTL coding standards.

Skills

RTL Design

SystemVerilog

Verilog

Microarchitecture

SoC blocks

ASIC design flow

RTL coding

Synthesis

Lint

CDC

STA

PPA optimization

Timing closure

Cross-functional teams

Job description

Role: Senior / Lead / Principal RTL Design Engineer

Job Overview

We are looking for experienced RTL Design Engineers with a strong background in Microarchitecture and Digital Design to work on complex semiconductor designs. The ideal candidate should have strong hands‑on experience taking designs from microarchitecture/specification through RTL implementation, verification, synthesis and sign‑off.

Key Responsibilities

• Understand and contribute to microarchitecture specifications and design requirements.
• Design and implement complex IP, subsystem, SoC, CPU/GPU or processor blocks.
• Participate in microarchitecture definition, design reviews and RTL architecture discussions.
• Develop optimized RTL considering performance, power, area (PPA) and design complexity.
• Work closely with Architecture, Verification, Physical Design and STA teams.
• Perform RTL simulation, debugging and functional issue resolution.
• Support lint, CDC, synthesis, STA and other design‑quality checks.
• Analyze and resolve timing, area, power and functional issues.
• Drive design closure and support integration of RTL blocks into larger SoC designs.
• Mentor junior engineers and contribute to RTL coding standards and design methodologies.

Required Skills

• 7–20+ years of experience in RTL Design / Digital Design.
• Strong hands‑on experience with Verilog/SystemVerilog.
• Strong understanding of Microarchitecture and Digital Logic Design.
• Experience in designing complex IP/SoC/subsystem blocks.
• Good understanding of ASIC design flow from specification to implementation.
• Strong knowledge of RTL coding, synthesis, lint, CDC and STA.
• Experience with PPA optimization and timing closure.
• Strong debugging and problem‑solving skills.
• Experience working with cross‑functional teams including DV, Architecture and Physical Design.

Preferred / Good to Have

• Experience with CPU, GPU, AI/ML accelerators, interconnects or high‑speed interfaces.
• Experience in ARM/processor‑based SoC designs.
• Knowledge of low‑power design methodologies.
• Experience with formal verification and design‑quality checks.
• Experience leading RTL design teams or mentoring engineers.

Candidate Profile

Candidates should have a strong microarchitecture foundation, excellent RTL coding skills, and experience owning complex blocks from microarchitecture through RTL and design closure.