Rtl Design Engineer

Alpha-Numero (A Quest Global Company); Ahmedabad District; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Alpha-Numero (A Quest Global Company) in Ahmedabad, Gujarat is seeking an experienced ASIC RTL Design Engineer to lead RTL work for complex digital systems. You will work on Verilog/SystemVerilog, debug flows, and collaborate across design, verification and physical teams to deliver robust RTL blocks.

The role requires hands-on ownership of RTL blocks, strong problem solving, and the ability to communicate technical concepts clearly with cross-functional teams.

Qualifications

• Hands-on experience in ASIC RTL design, IP design, debugging, RTL development, integration and bug fixes.
• Strong understanding of digital design fundamentals, RTL coding and ASIC design methodologies.
• Proven experience developing synthesizable RTL for complex digital systems.

Skills

Verilog/SystemVerilog

RTL design

Digital design fundamentals

Simulation

Debugging

Synthesis

Power, performance, area (PPA)

Problem solving

Documentation

Cross-functional collaboration

Job description

Role: ASIC RTL Design

Experience Required: 8+ years

Requirements:

• Hands-on experience in ASIC RTL design, IP Design, Debug, RTL Development, integration, Bug fixes.
• Strong understanding of digital design fundamentals, RTL coding, and ASIC design methodologies.
• Proven experience developing synthesizable RTL for complex digital systems.
• Strong proficiency in Verilog/SystemVerilog and RTL design practices.
• Experience with simulation, debugging, linting, CDC, synthesis, and other RTL design-quality processes.
• Good understanding of ASIC development flows and collaboration across design, verification, and physical design teams.
• Ability to analyze complex technical problems and develop efficient, reliable solutions.
• Strong understanding of design trade-offs involving power, performance, and area (PPA).
• Excellent problem-solving, communication, and technical documentation skills.
• Ability to work independently while collaborating effectively with cross-functional engineering teams.
• Senior Engineer candidates should demonstrate ownership of complex RTL blocks, while Architect-level candidates should have strong experience in microarchitecture, technical leadership, and design strategy.
• A strong passion for semiconductor technology and the ability to continuously learn and adapt to evolving ASIC design methodologies.