Senior ASIC RTL Design Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

SmartSoC, a Virtusa Company, seeks an experienced RTL Microarchitecture Lead to drive architecture and design of next-generation SoCs. Location: Bangalore/Hybrid or on-site in India with immediate availability.

You will own microarchitecture from specification to sign-off and collaborate with SoC, FPGA, DV, DFT, and Physical Design teams through tape-out. You will develop and review microarchitecture documents, deliver RTL and timing constraints, and guide IP sign-off.

Qualifications

• Strong expertise in ASIC RTL Design & Microarchitecture.
• Verilog / VHDL.
• RTL Development, Lint, UPF & Timing Constraints.
• SoC Integration & PPA Optimization.
• Experience with Verification, DFT & Physical Design flows.
• Version Control Systems (Git/Perforce).
• Scripting (TCL, Python, Perl or Shell).
• Experience collaborating with Firmware teams.

Responsibilities

• Drive SoC microarchitecture from specification to sign-off.
• Develop and review microarchitecture documents, including SoC Fabrics, IP Planning & Interfaces.
• Deliver RTL, UPF, and timing constraints in collaboration with design teams.
• Work closely with SoC, FPGA, DV, DFT, and Physical Design teams through implementation and tape-out.
• Review implementation plans and ensure design quality through final sign-off.
• Lead architecture reviews for IP sign-off and architecture feasibility.

Skills

ASIC RTL Design

Verilog/VHDL

RTL Development & UPF

SoC Integration

Verification & DFT

Git/Perforce

Scripting (TCL/Python/Perl)

Firmware collaboration

Education

B.E./B.Tech./M.E./M.Tech. in Electronics/Electrical/CS

Tools

Git

Perforce

Python

Job description

SmartSoC, a Virtusa Company, is a leading semiconductor engineering services organization specializing in end-to-end ASIC, SoC, FPGA, Embedded Systems, and VLSI design solutions. Backed by Virtusa's global engineering capabilities, SmartSoC partners with leading semiconductor companies to deliver innovative, high-quality silicon solutions across the entire chip development lifecycle.

We're looking for an experienced RTL Microarchitecture Lead to join our semiconductor team and drive the architecture and design of next-generation SoCs.

Availability: Immediate or currently serving notice candidates is preferred.

Location: Bangalore and Hyderabad

Key Responsibilities

• Drive SoC microarchitecture from specification to sign-off.
• Develop and review microarchitecture documents, including:
• SoC Fabrics & Protocol Bridges
• Fuse, Boot & Security Architecture
• IP Planning & Interfaces
• Pinout & Ball Mapping
• System & Test Planning
• Design Feasibility & PPA Analysis
• Develop microarchitecture to meet SoC performance, power, and area (PPA) targets.
• Author MAS/PRD documents and lead architecture reviews for IP sign-off.
• Deliver RTL, UPF, and timing constraints in collaboration with design teams.
• Work closely with SoC, FPGA, DV, DFT, and Physical Design teams through implementation and tape-out.
• Review implementation plans and ensure design quality through final sign-off.

Required Skills

• Strong expertise in ASIC RTL Design & Microarchitecture
• Verilog / VHDL
• RTL Development, Lint, UPF & Timing Constraints
• SoC Integration & PPA Optimization
• Experience with Verification, DFT & Physical Design flows
• Version Control Systems (Git/Perforce)
• Scripting (TCL, Python, Perl or Shell)
• Experience collaborating with Firmware teams

Preferred Profile

• Proven experience in architecting and delivering complex SoCs from concept to production.
• Strong understanding of RTL implementation, design sign-off, and semiconductor development lifecycle.
• Ability to drive cross-functional teams and technical reviews.

Qualification: B.E./B.Tech./M.E./M.Tech. in Electronics, Electrical Engineering, Computer Science, or a related field.