Staff Engineer - RTL

Cyient Limited; Telangana; Presencial; INR 1.400.000 - 2.300.000; Jornada completa

Descripción de la vacante

Cyient Limited in Telangana, India is seeking an experienced RTL Design Engineer to contribute to advanced digital building blocks for power management and low‑power applications. You will develop micro‑architecture specifications, implement RTL in VHDL/Verilog/SystemVerilog, and collaborate across firmware, verification, DFT and PD teams to meet timing and power goals.

The role requires 6–10 years of RTL experience, strong English communication, and hands‑on FPGA timing closure, UPF power

Formación

• 6–10 years of RTL development experience.
• Strong knowledge of VHDL/Verilog/SystemVerilog.
• Experience in conversion of ASIC RTL to FPGA RTL is a plus.

Responsabilidades

• Develop micro-architecture specifications for IPs and subsystems.
• RTL development using VHDL or Verilog/SystemVerilog.
• Lint, CDC, Synthesis and Power optimization.
• Identify and integrate soft and hard IP.
• Develop timing and power constraints.
• Collaborate with analog, firmware, verification and PD teams.
• Support FPGA clocking and multiple bit-file generation.
• Ensure FPGA timing closure and UPF implementation.
• Communicate progress clearly in English.

Conocimientos

RTL design

VHDL

Verilog

SystemVerilog

FPGA timing closure

Low power design

Power optimization

Team collaboration

English communication

Herramientas

FPGA Clock Wizard

Descripción del empleo

Designs advanced digital building blocks for various applications, including (but not limited to) power management, low-power & low-voltage applications.

Responsibilities:

• Micro-architecture specification development IP or Sub-System and design documentation
• RTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Timing and power constraints development
• Collaboration with analog design team for mixed-signal designs
• Collaboration with verification team in verification plan development and debug
• Collaboration with physical design team to close the design on timing and power
• Collaboration with firmware design team to close the design system scenarios
• 6 : 10 years' experience in RTL development
• Advanced knowledge of RTL design using VHDL or Verilog/SystemVerilog
• Low power (UPF) implementation. RTL sing-off.
• Experience working closely with Firmware, Verification, DFT & PD team
• Strong communication and presentation skills in English.
• Engineer must have good understanding on conversion of ASIC RTL to FPGA RTL.
• Experience in design partition on FPGA to generate multiple bit file, have good understanding on FPGA clock wizard configuration and building clock tree structure in FPGA.
• Experience in FPGA timing closure must.

Preferred Qualification:

• Hands-on experience with synthesis.
• Able to work in a team
• Good problem solving skills and being able to implement solutions autonomously
• Knowledge of mixed signal concepts (added advantage)