Senior Analog/Custom Layout Engineer

Acesoft Labs; Hyderabad; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Acesoft Labs in Hyderabad is seeking an Analog Custom Layout Engineer with 5–8 years of hands-on experience in analog and mixed-signal layout. The role requires expertise in full-chip integration and collaboration with multiple engineering teams.

Mandatory TSMC 3nm experience and strong skills in Cadence VLE/VXL and Calibre DRC/LVS will be essential. BE/MTech in Electronics or VLSI Engineering is expected.

Qualifications

• BE/MTech in Electronics or VLSI Engineering with minimum 5 years of hands-on analog/custom layout design.
• Proficiency with Cadence VLE/VXL and Calibre DRC/LVS; strong analog/custom layout techniques.
• TSMC 3nm experience is mandatory; exposure to 5/7/16nm FinFET is a plus.

Responsibilities

• Design and development of critical analog, mixed-signal, custom digital blocks and full-chip level integration.
• Perform layout verification (LVS, DRC, Antenna), quality checks, and documentation support.
• Ensure on-time delivery of block-level layouts with high quality and accuracy.
• Collaborate with engineering teams to ensure success of layout projects across multiple initiatives.
• Demonstrate strong problem-solving capabilities in physical verification.
• Mentor and guide junior team members in sub-block level layout execution and review.
• Support project management activities and milestone tracking.

Skills

Analog/layout design

Layout verification

CMOS techniques

Education

BE/MTech in Electronics or VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Position

Analog Custom Layout Engineer

Experience

5 to 8 Years

Location

Hyderabad

Industry

Semiconductor / VLSI

Technology Node

TSMC 3nm experience is mandatory, exposure to 5nm/7nm/16nm FinFET is a plus.

Key Responsibilities

• Design and development of critical analog, mixed-signal, custom digital blocks, and full-chip level integration.
• Perform layout verification (LVS, DRC, Antenna rule checks), quality checks, and documentation support.
• Ensure on-time delivery of block-level layouts with high quality and accuracy.
• Collaborate with engineering teams to assure the success of layout projects across multiple projects.
• Demonstrate strong problem-solving capabilities in physical verification.
• Mentor and guide junior team members in sub-block level layout execution and review of critical design elements.
• Support project management activities and milestone tracking.

Technical Skills

• Layout Tools: Cadence VLE/VXL
• Verification Tools: Mentor Graphics Calibre (DRC/LVS)
• Physical Verification: DRC, LVS, Antenna checks
• Technology Nodes: TSMC 3nm (mandatory), 5nm, 7nm, 16nm FinFET
• Strong understanding of analog/custom layout techniques in advanced CMOS processes

Educational Qualification

• BE/MTech in Electronics or VLSI Engineering
• Minimum 5 years of hands-on experience in analog/custom layout design