Analog Layout Engineer

leadIC Design Pvt Ltd; Bengaluru; On-site; INR 900,000 - 2,700,000; Full time

Job summary

leadIC Design Pvt Ltd is actively seeking an experienced Analog Layout Engineer to join our semiconductor design team. You will work on high-performance analog and mixed-signal IPs using advanced CMOS/FinFET technology nodes.

Ideal candidates have hands-on full-custom analog layout experience, preferably with TSMC nodes, and a strong grasp of matching, parasitics, and physical verification to deliver silicon-ready layouts.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or related field.
• 4–10 years of hands-on Analog/Mixed-Signal IC Layout experience.
• Strong experience in full-custom analog layout.
• Hands-on experience with TSMC technology nodes.
• Experience with 16nm and below nodes is highly preferred.
• Strong understanding of analog layout fundamentals and matching.
• Experience with DRC/LVS/ERC and physical verification.
• PEX and post-layout simulation/debugging experience.
• Ability to take blocks from schematic to layout to verification to tapeout.

Responsibilities

• Develop full-custom analog and mixed-signal layouts for complex IC designs.
• Layout analog building blocks like Op-Amps, Bandgap references, LDOs/Regulators, ADC/DAC, PLL/DLL, Charge Pumps, References, high-speed I/O and SerDes/DDR PHYs.
• Apply advanced layout techniques: symmetry, matching, guard rings, shielding, noise isolation.
• Perform parasitic-aware layout optimization and minimize routing/parasitics impact.
• Collaborate with analog designers to translate schematics into optimized layouts.
• Conduct DRC, LVS, ERC checks and debug layout issues.
• Support PEX/post-layout simulation and optimize layouts based on extracted parasitics.
• Ensure layouts meet area, matching, noise, reliability, EM/IR and performance goals.
• Work with TS​MC technology nodes including FinFET processes.

Skills

Full-custom analog layout

Matching

Parasitics

Analog/digital integration

Layout techniques

DRC/LVS/ERC

Post-layout verification

PEX/post-layout simulation

Education

Electrical/Electronics Engineering, Bachelors/Masters

Tools

Cadence Layout XL

Calibre

PVS / Assura

StarRC / Quantus

Job description

We are looking for an experienced Analog Layout Engineer to join our semiconductor design team and work on high-performance analog and mixed-signal IPs in advanced CMOS/FinFET technology nodes.

The ideal candidate should have strong hands-on experience in full-custom analog layout, preferably with TSMC technology nodes, and a solid understanding of matching, parasitics, advanced layout techniques, and physical verification.

The role involves working closely with analog circuit designers, physical verification, and other cross-functional teams to deliver high-quality, silicon-ready layouts.

Key Responsibilities

• Develop full-custom analog and mixed-signal layouts for complex IC designs.
• Work on layout of analog building blocks such as:
• Op-Amps
• Bandgap references
• LDOs / Regulators
• ADC/DAC blocks
• PLL/DLL
• Charge Pumps
• Current/Voltage References
• High-speed I/O and SerDes/DDR PHY circuits
• Implement advanced layout techniques including:
• Symmetry
• Matching
• Guard rings
• Shielding
• Sensitive-node isolation
• Perform parasitic-aware layout optimization and minimize the impact of routing and device parasitics on circuit performance.
• Work closely with analog designers to understand circuit requirements and translate schematics into optimized physical layouts.
• Perform DRC, LVS, ERC and other physical verification checks and debug layout issues.
• Support PEX/post-layout simulation and optimize layouts based on extracted parasitics.
• Ensure layouts meet requirements for area, matching, noise, reliability, EM/IR and performance.
• Work with advanced TSMC technology nodes, including FinFET-based processes.
• Collaborate with circuit design, verification, reliability, and physical design teams throughout the development cycle.
• Support IP integration, top-level layout, tapeout activities, and design documentation.
• Participate in layout reviews and contribute to improving layout methodologies and productivity.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or related field.
• 4–10 years of hands-on experience in Analog/Mixed-Signal IC Layout.
• Strong experience in full-custom analog layout.
• Hands-on experience with TSMC technology nodes is required.
• Experience in advanced technology nodes, preferably 16nm and below, will be highly preferred.
• Strong understanding of:
• Analog layout fundamentals
• Device matching
• Parasitic effects
• Analog routing techniques
• Noise isolation
• Reliability considerations
• Strong experience with DRC/LVS/ERC and physical verification.
• Experience with PEX and post-layout simulation/debugging.
• Ability to independently take blocks from schematic > layout > verification > tapeout.

Tools & Technology

Preferred tools:

• Cadence Layout XL
• Calibre
• PVS / Assura
• StarRC / Quantus or equivalent extraction tools

Technology:

• TSMC CMOS / FinFET nodes
• Preferably TSMC 16nm, 12nm, 7nm, 5nm and below

Preferred Experience

Candidates with experience in layout for the following will be preferred:

• SerDes PHY
• DDR / LPDDR PHY
• High-speed I/O
• PLL / DLL / CDR
• ADC / DAC
• Power Management ICs
• High-speed analog/mixed-signal circuits

Experience with high-speed interface PHYs and advanced FinFET nodes will be an added advantage.

• Strong analog layout fundamentals
• Physical verification/debugging
• Ability to work independently
• Good collaboration with circuit designers and verification teams