Custom/Analog Layout

Weekday AI (YC W21); Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Weekday AI invites an experienced Custom/Analog Layout Engineer to join our Hyderabad team. You will translate schematic designs into meticulous analog and mixed-signal layouts, ensuring performance, area efficiency, and manufacturability.

You will work closely with circuit designers and technology teams to optimize layouts, apply advanced techniques, and verify with DRC/LVS and parasitic extraction for robust tape-out readiness.

Qualifications

• Must have 4+ years hands-on experience in analog and mixed-signal layout.
• Strong expertise in translating schematics to high-quality layouts.
• Experience with layout verification, DRC/LVS, and parasitic extraction.

Responsibilities

• Design and develop analog and custom layouts for ICs based on schematics.
• Perform complete analog layout implementation for blocks (amplifiers, ADCs/DACs, PLLs).
• Apply advanced layout techniques (centroid, symmetry, matching, shielding).
• Collaborate with circuit designers to address parasitics and layout-dependent effects.
• Ensure layouts comply with foundry PDKs, process files, and design rules.

Skills

Analog Layout

Custom Layout

Parasitic Extraction

DRC LVS

Foundry PDKs

CMOS Tech

Education

Bachelors in Electronics/Microelectronics

Masters in VLSI Design

Tools

Layout Tools

DRC/LVS Tools

Parasitic Extraction

Job description

This role is for one of Weekday's clients

Salary range: Rs 1200000 - Rs 1800000 (ie INR 12 - 18 LPA)

Min Experience: 4+ years

Location: Hyderabad

JobType: full-time

We are looking for an experienced and detail-oriented Custom/Analog Layout Engineer with 4-11 years of hands‑on experience in semiconductor physical design. The ideal candidate will have strong expertise in Analog Layout and Custom Layout, with a solid understanding of analog and mixed‑signal circuit requirements, layout methodologies, and advanced semiconductor process technologies.

In this role, you will be responsible for translating circuit schematics into high‑quality physical layouts while ensuring performance, reliability, area efficiency, and manufacturability. You will work closely with circuit designers, physical design engineers, and technology teams to develop layouts for complex analog and custom blocks.

Key Responsibilities

• Design and develop custom and analog layouts for semiconductor devices and integrated circuits based on schematics and design specifications
• Perform complete Analog Layout implementation for blocks such as amplifiers, ADCs/DACs, PLLs, bandgaps, references, regulators, oscillators, and other analog/mixed‑signal circuits
• Develop high‑quality Custom Layout using appropriate layout techniques and process‑specific design rules
• Apply advanced layout techniques including common‑centroid, interdigitation, symmetry, matching, shielding, guard rings, dummy devices, and differential routing
• Analyze circuit requirements and translate electrical constraints into optimized physical layouts
• Perform Design Rule Check (DRC), Layout Versus Schematic (LVS), and parasitic extraction and resolve related issues
• Work with circuit designers to identify and address layout‑dependent effects, parasitics, matching issues, and performance degradation
• Optimize layouts for area, power, signal integrity, noise, matching, and overall circuit performance
• Participate in post‑layout simulations and troubleshoot issues related to parasitic resistance and capacitance
• Ensure layouts comply with foundry‑specific process design kits (PDKs), technology files, and design methodologies
• Collaborate with cross‑functional teams throughout the design, verification, and tape‑out process
• Maintain accurate documentation and follow established layout quality and verification standards

Must‑Have Skills

• Strong hands‑on experience in Analog Layout
• Strong expertise in Custom Layout
• 4-11 years of relevant experience in semiconductor/VLSI layout design
• Good understanding of analog and mixed‑signal circuit concepts
• Strong knowledge of layout‑dependent effects, device matching, parasitics, and physical design considerations
• Hands‑on experience with DRC, LVS, and parasitic extraction
• Experience working with industry‑standard custom layout and verification tools
• Ability to interpret schematics and understand circuit‑level design requirements
• Strong understanding of CMOS technologies and semiconductor fabrication concepts
• Experience working with foundry PDKs and technology‑specific design rules
• Strong debugging and problem‑solving skills with attention to layout quality and detail

Good‑to‑Have Skills

• Experience with advanced‑node technologies and complex analog/mixed‑signal designs
• Exposure to high‑speed, RF, memory, or power‑management layouts
• Knowledge of post‑layout simulation and parasitic‑aware circuit optimization
• Experience supporting full‑chip integration and tape‑out activities
• Familiarity with automation or scripting for layout‑related tasks

Education

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI Design, Microelectronics, or a related discipline.