Senior Analog Layout Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru, India, is seeking a Senior Analog Layout Engineer with strong hands-on expertise in custom/analog layout for cutting-edge technology nodes. You will own block-level analog/custom layouts from floorplanning to physical verification, develop layouts for analog, mixed-signal, and custom circuits, and work on 2nm/3nm/5nm nodes.

The role requires mastery of matching techniques, parasitics optimization, DRC/LVS/PEX, and collaboration with Analog, Circuit, and

Qualifications

• Hands-on analog/custom layout expertise.
• Experience with 2nm/3nm/5nm nodes.
• Strong understanding of layout fundamentals, matching, parasitics, and physical verification.

Responsibilities

• Own block-level analog/custom layout from floorplanning to physical verification.
• Develop high-quality layouts for analog, mixed-signal, and custom circuits.
• Work on 2nm/3nm/5nm technology nodes.
• Apply advanced matching, symmetry, common-centroid, shielding, and sensitive-net routing techniques.
• Optimize layouts for PPA, parasitics, IR drop, EM, and signal integrity.
• Perform DRC, LVS, ERC, PEX and resolve physical verification issues.
• Analyze and mitigate RC parasitics and layout-dependent effects (LDE).
• Collaborate with Analog Design, Circuit Design, and Physical Design teams.

Skills

Cadence Virtuoso

Advanced-node analog/layout

FinFET/GAA concepts

Matching techniques

Post-layout verification

Education

B.E./B.Tech in ECE/EEE/VLSI

Tools

Calibre/PVS

Job description

We are looking for a Senior Analog Layout Engineer with strong hands-on expertise in custom/analog layout for advanced technology nodes. The ideal candidate should have experience working on 2nm/3nm/5nm designs and a strong understanding of layout fundamentals, matching, parasitics, and physical verification.

Key Responsibilities

• Own block-level analog/custom layout from floorplanning to physical verification.


• Develop high-quality layouts for analog, mixed-signal, and custom circuits.


• Work extensively on 2nm/3nm/5nm technology nodes.


• Apply advanced matching, symmetry, common-centroid, shielding, and sensitive-net routing techniques.


• Optimize layouts for PPA, parasitics, IR drop, EM, and signal integrity.


• Perform DRC, LVS, ERC, PEX and resolve physical verification issues.


• Analyze and mitigate RC parasitics and layout-dependent effects (LDE).


• Collaborate closely with Analog Design, Circuit Design, and Physical Design teams.

Core Technical Skills

• Strong hands-on experience in Cadence Virtuoso / Custom Layout.


• Expertise in advanced-node analog/custom layout — 2nm/3nm/5nm.


• Strong knowledge of FinFET/GAA layout concepts and advanced-node design rules.


• Deep understanding of matching, shielding, guard rings, isolation, and parasitic optimization.


• Proficiency in Calibre/PVS and physical verification flows.


• Experience with PEX and post-layout simulation/correlation.

Qualifications

• B.E./B.Tech/M.E./M.Tech in ECE/EEE/VLSI or related discipline.


• 5–10 years of relevant Analog/Custom Layout experience.


• Proven experience delivering tapeout-quality layouts at advanced technology nodes.