Analog Layout Engineer

Digicomm Semiconductor INC; Bengaluru, Pune District, Hyderabad, Dadri; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

Digicomm Semiconductor INC is seeking an experienced Analog/Mixed-Signal Layout Engineer in Bengaluru. The role requires hands-on layout in advanced FinFET processes (16nm–3nm), expertise in PNR flow, CTS, routing, and timing closure.

You will work on critical blocks such as SERDES, PHY, HDMI, PLL, ADC, and DAC, ensuring robust physical verification and IP integration across full-chip designs. Candidates should possess strong leadership and communication skills to mentor a team and deliver

Qualifications

• Excellent work experience in Analog / Mixed Signal Layout design in FinFET processes (16nm–3nm).
• Expertise on complete PNR flow CTS, routing, Timing Closure.
• Hands-on experience in blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc.
• Strong understanding of CMOS/Bi-CMOS/SOI/FinFET processes.
• AMS IP integration in full chip per Full Chip guidelines.
• Proven ability to address routing congestion and physical verification challenges.
• Knowledge of DRC/LVS/ ERC/ Antenna/ LPE/ DFM verifications.
• Awareness of how layout affects speed, capacitance, power, noise, and area.

Responsibilities

• Lead and mentor layout team to ensure timely, high-quality custom layout execution.
• Review outputs for quality and delivery and guide junior members.
• Coordinate with design teams to align layout with full-chip requirements and constraints.

Skills

Analog Layout

Mixed-Signal Layout

PNR Flow

Routing

Timing Closure

AMS IP Integration

Physical Verification

Layout Techniques

Problem Solving

Team Leadership

Education

B.Tech / M.Tech in Electronics / VLSI

Tools

Cadence

Mentor

VirtuosoXL

Job description

• Qualifications : BTECH/MTECH

Job Description

• Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm
• Expertise on complete PNR flow CTS,routing, Timing Closure.
• Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
• Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
• Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
• Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs
• Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout
• Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc.
• Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area
• Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL
• Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and delivery
• Responsible for timely and quality execution of Custom Layout design
• Excellent communication skills and proactive at work