Analog Design Engineer

HighPoints Technologies India (P) Ltd; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Health insurance

Job summary

HighPoints Technologies India (P) Ltd in Hyderabad is seeking an experienced analog layout engineer to contribute to advanced CMOS designs. You will lead floorplanning, placement, routing, DRC/LVS checks and reliability considerations for nodes ranging from 2nm to 14nm, focusing on analog/mixed-signal blocks.

You should be proficient with Virtuoso, XL/EXL, IC12.1 and Calibre, and you’ll work with cross-functional teams to tackle sub-micron challenges like EM/ESD and crosstalk while delivering

Qualifications

• Experience in standard analog layout techniques for CMOS designs.
• Strong understanding of physical and electrical layout aspects.
• Experience with reliability physics including EM/ESD and crosstalk.
• Familiarity with latest nodes (2nm–14nm) and analog/mixed-signal blocks.

Responsibilities

• Layout CMOS designs with floorplan, placement and routing.
• Ensure DRC/LVS compliance and reliability considerations.
• Collaborate with design and process teams to optimize layouts.
• Address deep sub-micron challenges and yield-related issues.

Skills

Analog layout

Physical design

Layout techniques

EM/ESD reliability

Sub-micron challenges

Education

Bachelor's in Electrical Engineering or related

Tools

Virtuoso

XL/EXL

IC12.1

Calibre

Job description

Layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc

Expertise on 2nm,3nm,5nm,7nm,14nm etc technology nodes on various analog mixed signal blocks such as HBM, PLL, Band gap, LDO, ADC, DAC, SERDES, IO etc

Should be well versed with tools such as Virtuoso/ XL/ EXL, IC12.1, and Calibre etc

Requires excellent teamwork, good communication and strong problem-solving skills

Standard analog layout techniques and good understanding of physical, electrical aspects of layout

Good understanding of reliability physics including EM, ESD, crosstalk, shielding, Latchup and deep sub-micron challenges