Analog Layout Engineer

leadIC Design Pvt Ltd; Bengaluru; On-site; INR 2,600,000 - 4,800,000; Full time

Job summary

leadIC Design Pvt Ltd seeks an experienced Analog Layout Engineer to join our semiconductor design team in Bengaluru. You will work on high‑performance analog and mixed‑signal IPs using advanced CMOS/FinFET processes.

You will develop full‑custom analog layouts, collaborate with circuit designers, and perform parasitic-aware optimizations along with DRC/LVS/ERC verification and post-layout simulation.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or related field.
• 4–10 years of hands-on Analog/Mixed-Signal IC Layout experience.
• Strong experience in full-custom analog layout.
• Hands-on experience with TSMC technology nodes.
• Experience in advanced tech nodes, preferably 16nm and below.
• Strong understanding of analog layout fundamentals, device matching, parasitics, and routing techniques.
• Experience with DRC/LVS/ERC and physical verification.
• Experience with PEX and post-layout simulation/debugging.
• Ability to take blocks from schematic → layout → verification → tapeout.

Responsibilities

• Develop full-custom analog and mixed-signal layouts for complex IC designs.
• Layout analog building blocks such as Op-Amps, Bandgap refs, LDOs, ADC/DAC, PLL/DLL, and high-speed I/O blocks.
• Implement advanced layout techniques: symmetry, matching, guard rings, shielding, and isolation.
• Perform parasitic-aware layout optimization to minimize parasitics.
• Collaborate with analog designers to translate schematics into optimized layouts.
• Conduct DRC, LVS, ERC and other physical verification checks and debug issues.
• Support PEX/post-layout simulation and optimize layouts based on parasitics.
• Ensure layouts meet area, noise, reliability, EM/IR and performance targets.
• Work with TSMC technology nodes (FinFET) and cross-functional teams.

Skills

full-custom analog layout

analog/mixed-signal IC layout

layout optimization

parasitic awareness

matching fundamentals

noise isolation

design-for-verification

Education

Electrical/Electronics Engineering / VLSI degree

Tools

Cadence Layout XL

Calibre

PVS / Assura

StarRC / Quantus extraction

Job description

We are looking for an experienced Analog Layout Engineer to join our semiconductor design team and work on high-performance analog and mixed-signal IPs in advanced CMOS/FinFET technology nodes.

The ideal candidate should have strong hands-on experience in full-custom analog layout, preferably with TSMC technology nodes, and a solid understanding of matching, parasitics, advanced layout techniques, and physical verification.

The role involves working closely with analog circuit designers, physical verification, and other cross-functional teams to deliver high-quality, silicon-ready layouts.

Key Responsibilities

• Develop full-custom analog and mixed-signal layouts for complex IC designs.
• Work on layout of analog building blocks such as:
• Op-Amps
• Bandgap references
• LDOs / Regulators
• ADC/DAC blocks
• PLL/DLL
• Charge Pumps
• Current/Voltage References
• High-speed I/O and SerDes/DDR PHY circuits
• Implement advanced layout techniques including:
• Symmetry
• Matching
• Guard rings
• Shielding
• Sensitive-node isolation
• Perform parasitic-aware layout optimization and minimize the impact of routing and device parasitics on circuit performance.
• Work closely with analog designers to understand circuit requirements and translate schematics into optimized physical layouts.
• Perform DRC, LVS, ERC and other physical verification checks and debug layout issues.
• Support PEX/post-layout simulation and optimize layouts based on extracted parasitics.
• Ensure layouts meet requirements for area, matching, noise, reliability, EM/IR and performance.
• Work with advanced TSMC technology nodes, including FinFET-based processes.
• Collaborate with circuit design, verification, reliability, and physical design teams throughout the development cycle.
• Support IP integration, top-level layout, tapeout activities, and design documentation.
• Participate in layout reviews and contribute to improving layout methodologies and productivity.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or related field.
• 4–10 years of hands-on experience in Analog/Mixed-Signal IC Layout.
• Strong experience in full-custom analog layout.
• Hands-on experience with TSMC technology nodes is required.
• Experience in advanced technology nodes, preferably 16nm and below, will be highly preferred.
• Strong understanding of:
• Analog layout fundamentals
• Device matching
• Parasitic effects
• Analog routing techniques
• Noise isolation
• Reliability considerations
• Strong experience with DRC/LVS/ERC and physical verification.
• Experience with PEX and post-layout simulation/debugging.
• Ability to independently take blocks from schematic → layout → verification → tapeout.

Tools & Technology

Preferred tools:

• Cadence Layout XL
• Calibre
• PVS / Assura
• StarRC / Quantus or equivalent extraction tools

Technology:

• TSMC CMOS / FinFET nodes
• Preferably TSMC 16nm, 12nm, 7nm, 5nm and below

Preferred Experience

Candidates with experience in layout for the following will be preferred:

• SerDes PHY
• DDR / LPDDR PHY
• High-speed I/O
• PLL / DLL / CDR
• ADC / DAC
• Power Management ICs
• High-speed analog/mixed-signal circuits

Experience with high-speed interface PHYs and advanced FinFET nodes will be an added advantage.

• Strong analog layout fundamentals
• Physical verification/debugging
• Ability to work independently
• Good collaboration with circuit designers and verification teams