Senior AMS Layout Engineer

Insemi Technology Services; Dadri, Bengaluru; Presencial; INR 1.000.000 - 1.800.000; Jornada completa

Descripción de la vacante

Insemi Technology Services in India is seeking an experienced Analog Layout Engineer to contribute to full-custom analog/mixed-signal design. You will work on floorplanning, placement, routing, and verification for deep-submicron nodes, with emphasis on matching, shielding, and reliability.

The role requires 3–10 years of hands-on layout experience, proficiency with Cadence Virtuoso and Calibre, and collaboration with circuit teams to realize schematic intent in layout.

Formación

• 3+ years of experience in analog/mixed-signal layout
• Experience with full-custom layout
• Knowledge of matching techniques and symmetry
• Experience with deep submicron nodes (28nm or below)

Responsabilidades

• Design full-custom layouts for analog/mixed-signal blocks (LDO, PLL, ADC/DAC, IOs, etc.)
• Perform floorplanning, placement, routing, and optimization for area, power, and performance
• Ensure clean DRC, LVS, ERC, and antenna compliance
• Work closely with circuit/design teams to implement layout as per schematic intent
• Handle parasitic extraction (PEX) and support post-layout verification
• Apply matching techniques (common centroid, interdigitation)
• Address ESD, latch-up, and reliability concerns.

Conocimientos

Analog/mixed-signal layout

Floorplanning & routing

LDE, matching, symmetry

Deep submicron nodes (28nm+)

Herramientas

Cadence Virtuoso

Calibre DRC/LVS/PEX

Descripción del empleo

Job Title:

Analog Layout Engineer

Experience:

3 to 10 Years

Location:

Bangalore / Noida

Job Summary:

Looking for an experienced Analog Layout Engineer with 3+ years of expertise in full-custom analog/mixed-signal layout design. Experience in advanced technology nodes is preferred; exposure to 7nm nodes is an added advantage.

Key Responsibilities:

• Design full-custom layouts for analog/mixed-signal blocks (LDO, PLL, ADC/DAC, IOs, etc.)
• Perform floorplanning, placement, routing, and optimization for area, power, and performance
• Ensure clean DRC, LVS, ERC, and antenna compliance
• Work closely with circuit/design teams to implement layout as per schematic intent
• Handle parasitic extraction (PEX) and support post-layout verification
• Apply matching techniques (common centroid, interdigitation)
• Address ESD, latch-up, and reliability concerns.

Required Skills:

• Strong experience in analog/mixed-signal layout
• Hands‑on with Cadence Virtuoso, Calibre (DRC/LVS/PEX)
• Good understanding of LDE, matching, symmetry, shielding
• Experience in deep submicron nodes (28 nm or below preferred)

Good to Have:

• Experience in 7nm / FinFET technologies
• Knowledge of EM/IR, reliability checks
• Scripting (Skill/Python)