Analog Layout Engineer – Non-FinFET

Purna Semi; Bengaluru; Vor Ort; INR 900.000 - 1.500.000; Vollzeit

Zusammenfassung

Purna Semi in Bengaluru, India is seeking an experienced Analog/Mixed-Signal Layout Designer with 3–8 years of experience. You will contribute to AMS layout design, device matching, and layout signoff, ensuring robust DRC/LVS/PEX compliance and strong schematic-to-layout integration.

Experience with SMOS10HV process technology, high-voltage analog layout concepts, and PMIC/automotive mixed-signal IP are highly preferred.

Qualifikationen

• B.E./B.Tech / M.E./M.Tech in Electronics, VLSI, Microelectronics or related field.
• Hands-on experience with SMOS10HV process technology.
• Strong experience in Analog/Mixed-Signal (AMS) Layout Design.
• Analog layout methodologies & hierarchy-based implementation.
• Device matching, symmetry, common-centroid & interdigitated layouts.
• Guard rings, shielding & layout optimization.
• Strong schematic-to-layout understanding.
• Experience with DRC, LVS, PEX & layout signoff.

Kenntnisse

AMS Layout Design

Schematic-to-layout

DRC/LVS/PEX

Layout optimization

Device matching & centroid layouts

High-voltage layout concepts

Ausbildung

B.E./B.Tech / M.E./M.Tech in Electronics, VLSI, Microelectronics or related field

Tools

SMOS10HV process technology

Jobbeschreibung

Experience: 3-8 Yrs
Domain: Analog / Mixed-Signal Semiconductor

Required Skills:

• B.E./B.Tech / M.E./M.Tech in Electronics, VLSI, Microelectronics or related field
• Hands-on experience with SMOS10HV process technology
• Strong experience in Analog/Mixed-Signal (AMS) Layout Design
• Analog layout methodologies & hierarchy-based implementation
• Device matching, symmetry, common-centroid & interdigitated layouts
• Guard rings, shielding & layout optimization
• Strong schematic-to-layout understanding
• Experience with DRC, LVS, PEX & layout signoff

Preferred Skills:

• High-Voltage Analog Layout
• PMIC / Automotive Semiconductor / Mixed-Signal IP
• ESD & Latch-up protection concepts
• Post-layout simulation
• Reliability & manufacturability requirements