Ams Verification Engineer

Object Technology Solutions; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Object Technology Solutions is seeking an experienced hardware design engineer to work on building block schematics, memory schematics, and SPICE-based verification. You will decipher circuit behavior from schematics, perform DC and transient analyses, and conduct gate-level simulations with SDF back-annotation.

The role requires familiarity with Verilog MOS models, static timing analysis, and SystemVerilog assertions, with strong communication skills to collaborate with peers.

Qualifications

• Hands-on experience in developing/building block schematics and memory schematics.
• Experience in deciphering circuit behavior from schematics.
• Familiarity with circuit characterization, timing libraries - files and formats, timing arcs.
• Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
• Familiarity with static timing analysis.
• Hands-on experience in Gate level simulations with SDF back annotation.
• Debug SDF annotation issues and ensure good annotation coverage.
• Hands-on knowledge of latch based designs and their timing requirements.
• Debugging Gate level simulation failures and root-cause analysis.

Responsibilities

• Gate level simulation, spice correlation, debugging failures and fixes at gate or transistor level.
• What-if analysis by making changes and ensuring fixes solve the issue.
• SystemVerilog Assertions to specify expected design behavior.
• Communicate complex technical concepts to peers both verbally and in writing.

Skills

Circuit design

Circuit simulation

Spice simulators

DC analysis

Transient analysis

Schematic reading

Timing libraries

Timing arcs

Verilog MOS models

Netlist simulation

Delay simulation

Static timing analysis

Gate-level simulation

SDF back-annotation

SDF debugging

Latch timing

Debug failures

SystemVerilog Assertions

UVM

Communication skills

Job description

• ? Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
• ? Experience in deciphering circuit behavior from schematics.
• ? Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
• ? Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
• ? Familiarity with static timing analysis
• ? Hands-on experience in Gate level simulations with SDF back annotation.
• ? Debug SDF annotation issues and ensure good annotation coverage.
• ? Hands-on experience with latch based designs and their timing requirements.
• ? Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
• ? Hands-on knowhow of System Verilog Assertions to specify expected design behavior
• ? Familiarity with UVM is a plus
• ? Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
• ? Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable.