Hiring GLS Design Verification Engineers -HYD Mirafra Technologies

Mirafra; Hyderabad; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Mirafra in Hyderabad seeks an experienced circuit design engineer with 5–8 years of hands-on experience in building block schematics, memory schematics, and circuit simulations using SPICE. The role requires deciphering circuit behavior from schematics and performing timing analysis.

You will work on gate-level simulations, SDF back annotation, and debugging timing issues, with exposure to SystemVerilog Assertions. Strong communication is essential to share complex results with peers.

Qualifications

• 5–8 years of experience in circuit design and verification.
• Hands-on in building block schematics and memory schematics.
• Experience with SPICE, timing analysis, and SDF back annotation.
• Strong communication skills to convey complex concepts.

Responsibilities

• Develop/build block schematics and memory schematics.
• Run circuit simulations with SPICE.
• Decipher circuit behavior from schematics.
• Perform static timing analysis and gate-level simulations.
• Debug SDF annotation issues and ensure coverage.
• Use SystemVerilog Assertions to specify design behavior.
• Collaborate with design peers and communicate findings.

Skills

Verilog MOS models

Gate-level simulation

SPICE simulations

Static timing analysis

SystemVerilog Assertions

UVM

Debugging

Tools

SPICE simulators

SDF back annotation

Timing libraries

Job description

Location - Hyderabad

Exp - 2 to 8 yrs

Availability - 0 to 30 days

CCTC-

Exp CTC-

Notice Period -

CU Location -

Open to hyd -

Experience: 5yrs to 8yrs.

• Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
• Experience in deciphering circuit behavior from schematics.
• Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
• Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
• Familiarity with static timing analysis
• Hands-on experience in Gate level simulations with SDF back annotation.
• Debug SDF annotation issues and ensure good annotation coverage.
• Hands-on experience with latch based designs and their timing requirements.
• Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
• Hands-on knowhow of System Verilog Assertions to specify expected design behavior
• Familiarity with UVM is a plus
• Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
• Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable