Analog Mixed Signal Verification Engineer

Ciliconchip; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Ciliconchip in Bengaluru, India is seeking a Verification Lead for mixed-signal ICs. You will drive verification, create block-level models, and develop automated test benches to validate functionality and robustness.

Collaborating with application, analog and digital design leads, you will address issues, push for first-pass silicon success, and foster a collaborative, resilient team culture with strong communication and leadership.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or a related field, with 1 to 5 years of experience.
• Design Knowledge: Experience in analog or mixed-signal design verification, with proficiency in UVM-based methodologies
• Technical Expertise: Skilled in modeling analog mixed-signal blocks such as bandgap, oscillators, ADCs, DACs, LDOs, SerDES, DDR, GPIO.
• Tool Knowledge: Hands on experience on AMS verification Tools (Synopsys XA, Cadence DiscoveryAMS)
• EDA Tools: Knowledge of common tools like Cadence Virtuoso, Maestro, and vManager
• Scripting Skills: Proficiency in System Verilog, VAMS, or real-number modeling for designing and simulating verification models
• Soft Skills: Strong communication and leadership abilities, with the ability to persevere through challenges and drive root-cause analysis to closure

Responsibilities

• Verification Leadership: Drive the verification of mixed-signal ICs using best practices to ensure first-pass silicon success
• Model Creation: Create and verify block-level models (e.g., System Verilog, VAMS) for use in top-level mixed-mode simulations
• Test Development: Develop application-specific test benches with automated checkers to evaluate IC functionality and robustness
• Collaboration: Work closely with application, analog design, and digital design leads to verify system-level and IC-level functions and specifications
• Debug Support: Partner with the design team to analyze and address errors found during the verification process
• Team Culture: Foster a collaborative, innovative, and resilient team culture that encourages open communication

Skills

SystemVerilog

UVM

VAMS

AMS verification

Analog mixed-signal design

Leadership

Communication

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Synopsys XA

Cadence DiscoveryAMS

Cadence Virtuoso

Maestro

vManager

Job description

• Verification Leadership: Drive the verification of mixed-signal ICs using best practices to ensure first-pass silicon success
• Model Creation: Create and verify block-level models (e.g., System Verilog, VAMS) for use in top-level mixed-mode simulations
• Test Development: Develop application-specific test benches with automated checkers to evaluate IC functionality and robustness
• Collaboration: Work closely with application, analog design, and digital design leads to verify system-level and IC-level functions and specifications
• Debug Support: Partner with the design team to analyze and address errors found during the verification process
• Team Culture: Foster a collaborative, innovative, and resilient team culture that encourages open communication

Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering or a related field, with 1 to 5 years of experience.
• Design Knowledge: Experience in analog or mixed-signal design verification, with proficiency in UVM-based methodologies
• Technical Expertise: Skilled in modeling analog mixed-signal blocks such as bandgap, oscillators, ADCs, DACs, LDOs, SerDES, DDR, GPIO.
• Tool Knowledge: Hands on experience on AMS verification Tools (Synopsys XA, Cadence DiscoveryAMS)
• EDA Tools: Knowledge of common tools like Cadence Virtuoso, Maestro, and vManager
• Scripting Skills: Proficiency in System Verilog, VAMS, or real-number modeling for designing and simulating verification models
• Soft Skills: Strong communication and leadership abilities, with the ability to persevere through challenges and drive root-cause analysis to closure