Analog Mixed Signal Verification Engineer

UST; Bengaluru Urban; On-site; INR 5,000,000 - 7,000,000; Full time

Job summary

UST in Bengaluru, India is seeking a senior engineer to lead sub-system and full-chip AMS simulations. You will review SoC specifications, develop robust SPICE flows, and collaborate with cross-functional teams to debug circuit-level issues.

The role emphasizes CMOS device modelling, access to Cadence/Questa/ Spectre tools, and ongoing improvement of simulation methodologies for high‑quality SoCs.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering (EE/EC) or equivalent.
• 8+ years of relevant experience in AMS/analog simulations.
• Strong fundamentals in analog circuit analysis.
• Hands-on SPICE simulation experience.
• Experience with Cadence, Questa ADMS, Spectre, HSPICE or equivalent.
• Scripting experience with Perl, SKILL, TCL or equivalent is an advantage.

Responsibilities

• Perform sub-system, chip-level AMS, and SPICE simulations.
• Review and understand SoC specifications and design requirements.
• Perform ERC and PISI analysis to identify and resolve potential design issues.
• Develop and improve AMS simulation methodologies and flows.
• Collaborate with cross-functional design teams to analyze and debug circuit-level issues.
• Support the development and implementation of simulation flows for sub-system and full-chip designs.

Skills

Analog circuit analysis

SPICE simulations

Circuit debugging

Analytical problem solving

Scripting: Perl/TCL/Skill

Education

Bachelor’s or Master’s degree in Electrical/Electronics Engineering (EE/EC) or equivalent

Masters in EE/EC (preferred)

Tools

Cadence

Questa ADMS

Spectre

HSPICE

Job description

• Perform sub-system, chip-level AMS, and SPICE simulations.
• Review and understand SoC specifications and design requirements.
• Perform ERC and PISI analysis to identify and resolve potential design issues.
• Develop and improve AMS simulation methodologies and flows.
• Collaborate with cross-functional design teams to analyze and debug circuit-level issues.
• Support the development and implementation of simulation flows for sub-system and full-chip designs.

Job Requirements

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering (EE/EC) or equivalent, with 8+ years of relevant experience.
• Strong fundamentals in analog circuit analysis.
• Good understanding of CMOS device operation and characteristics.
• Hands-on experience with sub-system and full-chip SPICE simulations.
• Good understanding of analog macros, such as ADC/DAC, PLL, voltage regulators, bandgap references, comparators, and related circuits.
• Experience with circuit simulation tools such as Cadence, Questa ADMS, Spectre, HSPICE, or equivalent.
• Strong analytical, debugging, and problem-solving skills.
• Ability to explore and implement new simulation tools, methodologies, and flows for continuous improvement.
• Scripting experience with Perl, SKILL, TCL, or equivalent for simulation flow automation is an advantage.