Hiring AMS Verification Engineer - Mirafra Technologies HYD

Mirafra; Hyderabad; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Mirafra in Hyderabad, India seeks an experienced IC Design verification engineer to perform gate-level simulations, SPICE correlation, and debugging across the full flow from schematic to timing closure.

You will work on Verilog MOS switch level models, SDF back annotation, and SystemVerilog Assertions to specify designed behavior, with a focus on robust timing and debug capability.

Qualifications

• Experience deciphering circuit behavior from schematics and running circuit simulations with SPICE
• Hands-on experience with timing libraries, timing arcs and static timing analysis
• Proficient in gate level simulations, netlist simulations and zero/unit/path delay models
• Familiar with UVM, SystemVerilog Assertions, and debugging gate level and SPICE related issues
• Strong communication skills and ability to convey complex technical concepts clearly to peers

Responsibilities

• Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
• Experience in deciphering circuit behavior from schematics.
• Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
• Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
• Familiarity with static timing analysis
• Hands-on experience in Gate level simulations with SDF back annotation.
• Debug SDF annotation issues and ensure good annotation coverage.
• Hands-on experience with latch based designs and their timing requirements.
• Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
• Hands-on knowhow of System Verilog Assertions to specify expected design behavior
• Familiarity with UVM is a plus
• Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
• Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable

Skills

Verilog MOS models

SystemVerilog Assertions

Gate level simulation

SPICE simulations

Static timing analysis

SDF back-annotation

Latch-based timing

What-if analysis

Timing libraries

Timing arcs

Tools

SPICE simulators

SDF back-annotation

UVM

Job description

• Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
• Experience in deciphering circuit behavior from schematics.
• Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
• Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
• Familiarity with static timing analysis
• Hands-on experience in Gate level simulations with SDF back annotation.
• Debug SDF annotation issues and ensure good annotation coverage.
• Hands-on experience with latch based designs and their timing requirements.
• Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
• Hands-on knowhow of System Verilog Assertions to specify expected design behavior
• Familiarity with UVM is a plus
• Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
• Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable