Design Verification

Object Technology Solutions; Hyderabad; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Object Technology Solutions seeks an experienced circuit design engineer to contribute hands-on in building block schematics and running SPICE-based simulations. You will decipher circuit behavior, analyze timing, and work with gate-level simulations including SDF back-annotation.

Strong Verilog and SystemVerilog assertion skills are required. You will debug annotation issues, ensure timing coverage, and collaborate with design peers to diagnose root causes and propose fixes across latch-based

Qualifications

• Hands-on circuit design and simulation experience.
• Experience reading schematics and deciphering circuit behavior.
• Familiarity with SDF back-annotation and gate-level timing.
• Proficiency in Verilog and SystemVerilog assertions.
• Knowledge of spice-based simulations and timing analysis.

Responsibilities

• Develop/build block schematics and run DC/transient simulations.
• Decipher circuit behavior from schematics and verify timing.
• Characterize timing libraries and timing arcs in designs.
• Perform gate-level simulations with SDF back-annotation.
• Debug SDF annotation issues and ensure coverage.
• Work with latch-based designs and analyze timing requirements.
• Identify root causes from gate-level simulations and propose fixes.
• Apply SystemVerilog Assertions to specify expected design behavior.
• Collaborate with peers and communicate technical concepts clearly.

Skills

Digital circuit design

Gate level timing

Verilog

SystemVerilog Assertions

UVM (plus)

Circuit debugging

Tools

Spice simulators

SDF back-annotation

Verilog netlists

Timing libraries

Gate level simulation

Job description

Role & responsibilities

• ? Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
• ? Experience in deciphering circuit behavior from schematics.
• ? Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
• ? Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
• ? Familiarity with static timing analysis
• ? Hands-on experience in Gate level simulations with SDF back annotation.
• ? Debug SDF annotation issues and ensure good annotation coverage.
• ? Hands-on experience with latch based designs and their timing requirements.
• ? Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
• ? Hands-on knowhow of System Verilog Assertions to specify expected design behavior
• ? Familiarity with UVM is a plus
• ? Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
• ? Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable.