Subsystem & SoC Front-End RTL Engineer

ARM; Cambridge; In loco; GBP 70.000 - 120.000; Tempo pieno

Descrizione del lavoro

Arm is seeking a Front End design engineer to contribute to the specification, design and verification of subsystems and testchips within our Solution Engineering group. You will develop RTL, integrate IPs, and author design intent documents (SDC/UPF) while collaborating with verification and implementation teams to ensure timely delivery.

Ideal candidates will have strong SystemVerilog skills, experience with complex SoC architectures, and familiarity with UNIX scripting to support automation

Competenze

• Hands-on knowledge of System Verilog/Verilog HDL for RTL design.
• RTL design for complex SoC development.
• Experience in static design checks, power and clock domain crossing, synthesis.
• Strong understanding of computer architecture and systems fundamentals with hands-on experience in complex system design.
• Knowledge of UNIX environment and scripting eg Python, Perl or UNIX shell scripting.
• Ability to write specifications and documentation describing complex designs.

Mansioni

• Spec, design and verify subsystems and/or testchips as part of the design team.
• Develop RTL and design intent deliverables (SDC, UPF); integrate IPs; run design checks and draft micro-architecture specifications.
• Collaborate with verification to review test plans and aid debugging; work with implementation to optimise designs.
• Plan work, provide tracking and report status to ensure high-quality and timely delivery.

Conoscenze

SystemVerilog/Verilog HDL

RTL design for SoC

UNIX scripting

Formazione

Bachelor's degree in Electrical Engineering or related

Strumenti

UPF

SDC

Descrizione del lavoro

Arm is seeking a Front End design engineer to contribute to the specification, design and verification of subsystems and testchips within our Solution Engineering group. You will develop RTL, integrate IPs, and author design intent documents (SDC/UPF) while collaborating with verification and implementation teams to ensure timely delivery.

Ideal candidates will have strong SystemVerilog skills, experience with complex SoC architectures, and familiarity with UNIX scripting to support automation