Senior SoC Design Engineer - RTL & IP Integration

Arm Limited; West of England; Hybrid; GBP 70,000 - 100,000; Full time

Job summary

Arm Limited in the United Kingdom is seeking a skilled RTL engineer to join the SoC team developing processing systems for IoT, Automotive and Infrastructure computing. You will work with internal teams to optimise performance and power while integrating IPs and subsystems.

The role covers microarchitecture specifications, RTL design, verification planning, and collaboration with performance analysis. Candidates should have strong Verilog HDL, experience with synthesis and timing analysis, and a

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or equivalent.
• Experience in digital hardware design and Verilog HDL.
• Understanding of modern SoC development methods.
• Experience with CDC/RDC/X-prop and lint checks.
• Experience creating design specifications.
• Proficiency in Perl or Python or other scripting languages.
• Strong track record delivering RTL subsystems on schedule.
• Ability to perform high-level PPA trade-offs and justify choices.
• Experience with synthesis and timing analysis and power management.
• Good communication and collaboration skills.

Responsibilities

• Understand incoming IPs, interfaces and interwork with subsystem/SoC components; develop microarchitecture specifications and RTL.
• Review subsystem architecture, develop microarchitecture specifications, review verification plans and help debug issues.
• Work with the performance analysis team to evaluate and improve system performance.
• Guide and support other team members to enable successful completion of project activities while balancing tasks with Project Management.

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field

Tools

SystemVerilog

AMBA AXI / ACE-Lite

Job description

Arm Limited in the United Kingdom is seeking a skilled RTL engineer to join the SoC team developing processing systems for IoT, Automotive and Infrastructure computing. You will work with internal teams to optimise performance and power while integrating IPs and subsystems.

The role covers microarchitecture specifications, RTL design, verification planning, and collaboration with performance analysis. Candidates should have strong Verilog HDL, experience with synthesis and timing analysis, and a