Senior SoC Subsystem Design Architect

Arm Limited; Cambridge; Hybrid; GBP 70,000 - 100,000; Full time

Job summary

Arm Solution Engineering's Front End design team in Cambridge is seeking an experienced RTL design engineer to contribute to subsystem designs for GPU and other IP. You will develop RTL, SDC/UPF constraints, integrate IPs and work with verification and implementation teams to ensure high‑quality designs.

The role requires SystemVerilog/Verilog HDL skills, strong RTL design grounding, UNIX scripting, and collaboration across CPU, GPU, multimedia IP.

Qualifications

• Hands-on SystemVerilog or Verilog HDL for RTL design.
• Strong RTL design grounding for complex SoC development.
• Experience with design checks, clock domain crossing, and synthesis.
• Understanding of computer architecture and high‑performance peripherals.

Responsibilities

• Develop RTL and design intent deliverables (SDC, UPF) for subsystems.
• Integrate IPs, run design checks, and help refine micro‑architecture specs.
• Collaborate with verification to review test plans and debug designs.
• Plan work, track progress, and report status for timely delivery.

Skills

SystemVerilog

Verilog HDL

RTL design

SoC development

CPU/GPU/IP

UNIX scripting

Python

Documentation writing

Tools

Synthesis

Job description

Arm Solution Engineering's Front End design team in Cambridge is seeking an experienced RTL design engineer to contribute to subsystem designs for GPU and other IP. You will develop RTL, SDC/UPF constraints, integrate IPs and work with verification and implementation teams to ensure high‑quality designs.

The role requires SystemVerilog/Verilog HDL skills, strong RTL design grounding, UNIX scripting, and collaboration across CPU, GPU, multimedia IP.