Staff Subsystem RTL Architect

Arm; Cambridge; Hybrid; GBP 97,000 - 132,000; Full time

Job summary

Arm’s Solutions Engineering team in Cambridge seeks an experienced Staff Subsystem Design Engineer to design and integrate IP and subsystems for next-generation Edge AI, Physical AI, and Cloud AI platforms.

You will develop microarchitectures, verify designs, and collaborate with architecture, verification, implementation and power teams to meet timing, area and power targets. A strong track record in RTL/SoC design is essential.

Qualifications

• Bachelor’s/Master’s/PhD in Electrical Engineering, Electronics Engineering, Computer Engineering or related field.
• 10+ years of relevant industry experience.
• Extensive hands-on digital RTL design using SystemVerilog/Verilog.

Responsibilities

• Analyse architectural and system specifications and refine solutions with architects.
• Develop subsystem/IP microarchitecture specifications from high-level requirements.
• Design new IP/subsystem logic and integrate Arm and third-party IP.
• Understand IP interfaces and system interactions for robust integration.
• Develop and maintain design intent including UPF and timing constraints.
• Perform design quality checks: lint, CDC, RDC, X-propagation and synthesis.
• Collaborate with verification teams to review test plans and debug issues.
• Work with implementation, performance and power teams to meet requirements.
• Drive high-quality and timely delivery of work.

Skills

SystemVerilog

RTL design

Microarchitecture

IP integration

Synthesis

Timing analysis

Power management

UPF

AMBA AXI/APB

C/C++

EDA tools

Static checks

Education

Bachelor's/Master's/PhD in Electrical/Electronics/Computer Engineering

Tools

UVM

EDA tools

Job description

Arm’s Solutions Engineering team in Cambridge seeks an experienced Staff Subsystem Design Engineer to design and integrate IP and subsystems for next-generation Edge AI, Physical AI, and Cloud AI platforms.

You will develop microarchitectures, verify designs, and collaborate with architecture, verification, implementation and power teams to meet timing, area and power targets. A strong track record in RTL/SoC design is essential.