Staff Subsystem Design Engineer - RTL/IP Lead

Arm; Sheffield; Hybrid; GBP 97,000 - 132,000; Full time

Job summary

Arm’s IP and Technology team in Solutions Engineering is seeking a Staff Subsystem Design Engineer with a strong RTL and IP design background. You will develop subsystem and IP microarchitectures, design and integrate Arm and third-party IP, and collaborate across architecture, verification and implementation teams to deliver optimized subsystem solutions.

You will work on challenging designs, supporting power, performance and area trade-offs, while refining design intent, timing constraints,

Qualifications

• Hands-on RTL design and microarchitecture in SystemVerilog/Verilog.
• Strong track record in IP or RTL subsystem design.
• Experience with RTL techniques for complex SoC.
• Ability to translate high-level specs into microarchitectures.
• Familiarity with EDA tools and methodologies.
• Experience with Lint, CDC, RDC, X-propagation.

Responsibilities

• Analyse architectural specifications and refine solutions with architects.
• Develop subsystem and IP microarchitecture from high-level requirements.
• Design new IP and integrate Arm/third-party IP into subsystems.
• Ensure correct IP interfaces and system-level interactions.
• Develop design intent and timing constraints, where applicable.
• Conduct design quality checks such as synthesis and static checks.
• Collaborate with verification to review tests and debug issues.
• Work with implementation, power teams to meet requirements.
• Improve design methodologies and flows for IP development.
• Plan work to ensure high-quality, timely delivery.
• Provide technical guidance and participate in design reviews.

Skills

SystemVerilog

RTL design

SoC subsystems

AMBA AXI

Power timing

Python scripting

C/C++

Collaboration

Tools

EDA tools

Job description

Arm’s IP and Technology team in Solutions Engineering is seeking a Staff Subsystem Design Engineer with a strong RTL and IP design background. You will develop subsystem and IP microarchitectures, design and integrate Arm and third-party IP, and collaborate across architecture, verification and implementation teams to deliver optimized subsystem solutions.

You will work on challenging designs, supporting power, performance and area trade-offs, while refining design intent, timing constraints,