Senior SoC Subsystem Design Engineer

Arm; Cambridge; Hybrid; GBP 97,000 - 132,000; Full time

Job summary

Arm Solution Engineering delivers complex solutions from system specifications to silicon. Join our Front End design team within Arm's SE SoC Engineering to help develop complete subsystem designs for GPU, display, memory controllers and high-performance peripherals.

You will contribute to RTL development, IP integration and verification workflows, collaborating with design, verification and implementation teams to deliver high-quality testchips on schedule.

Qualifications

• Hands-on knowledge of System Verilog or Verilog HDL for RTL design.
• Strong RTL design for complex SoC development.
• Experience with static design checks, power and clock domain crossing, synthesis.
• Knowledge of computer architecture and systems fundamentals with CPU, GPU, multimedia IP.
• Familiar with UNIX environment and scripting (Python, Perl, or UNIX shell).
• Ability to write specifications and documentation describing complex designs.

Responsibilities

• Develop the RTL and design intent deliverables (SDC, UPF), integrating IPs.
• Run design checks and contribute to micro-architecture spec.
• Work with verification to review test plans and debug design issues.
• Collaborate with implementation to optimize designs.
• Plan work, provide status reports to ensure timely delivery.

Skills

SystemVerilog

RTL design

Synthesis

Power and clock domain crossing

CPU/GPU/multimedia IP

UNIX scripting

Documentation writing

Tools

Python

Perl

UNIX shell scripting

Job description

Arm Solution Engineering delivers complex solutions from system specifications to silicon. Join our Front End design team within Arm's SE SoC Engineering to help develop complete subsystem designs for GPU, display, memory controllers and high-performance peripherals.

You will contribute to RTL development, IP integration and verification workflows, collaborating with design, verification and implementation teams to deliver high-quality testchips on schedule.