RTL & Microarchitecture Lead for High-Speed Interconnect

CamWebDir; United Kingdom; Hybrid; GBP 110,000 - 190,000; Full time

Job summary

Arm is seeking a senior RTL and microarchitecture engineer to own the design of high-speed interconnect subsystems across multiple silicon products, including PCIe, CXL, and UALink. You will translate system requirements into microarchitecture specs, interfaces, and synthesizable RTL.

You will drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis readiness, and final delivery, collaborating with architecture, verification,

Qualifications

• 8+ years in RTL build, microarchitecture, subsystem integration or related semiconductor roles.
• Deep hands-on SystemVerilog expertise for high-performance digital subsystems.
• Strong knowledge of PCIe, CXL, UALink including memory and connectivity.

Responsibilities

• Own the microarchitecture, RTL development and integration of high‑speed interconnect subsystems across silicon products.
• Drive development from concept through RTL creation, verification support, and final delivery with cross‑functional collaboration.
• Lead technical reviews, mentor engineers and ensure timing, power, and performance targets are met.

Skills

RTL development

SystemVerilog

Microarchitecture

PCIe

CXL

UALink

AXI/CHI/ACE

Interconnects

Leadership

Memory systems

Education

BSc/MSc in EE/CE/CS

Tools

Verilog/VHDL

Synthesis tools

Job description

Arm is seeking a senior RTL and microarchitecture engineer to own the design of high-speed interconnect subsystems across multiple silicon products, including PCIe, CXL, and UALink. You will translate system requirements into microarchitecture specs, interfaces, and synthesizable RTL.

You will drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis readiness, and final delivery, collaborating with architecture, verification,