Senior Subsystem Design Engineer — RTL/IP Expert

Arm Limited; Cambridge, Manchester, West of England, Sheffield; Remote; GBP 110,000 - 150,000; Full time

Job summary

Arm Limited in Cambridge is seeking a Staff Subsystem Design Engineer to lead RTL and subsystem IP design for next-generation compute platforms. You will specify, microarchitect and integrate complex IP and subsystems, collaborating with architecture, verification, and implementation teams to ensure high-quality, power-efficient designs.

The role requires 10+ years in RTL design, strong SystemVerilog/Verilog skills, and experience with AMBA AXI/APB interfaces, SVA and UVM are advantageous.

Qualifications

• Bachelor’s, Master’s or PhD in Electrical/Electronics/Computer Engineering or related discipline.
• 10+ years of relevant industry experience.
• Experience with SystemVerilog/Verilog for RTL design.

Responsibilities

• Analyse architectural and system specifications and refine solutions with architects.
• Develop subsystem and IP microarchitecture specifications from high-level requirements.
• Design new IP and subsystem logic and integrate Arm and third-party IP.
• Understand IP functionality and system interfaces for robust integration.
• Develop design intent and timing constraints (UPF).
• Perform design quality checks including Lint, CDC, RDC, X-propagation and synthesis.
• Navigate trade-offs and document engineering decisions clearly.
• Support verification and debug with verification teams.
• Collaborate with implementation, performance and power teams to meet requirements.
• Improve design methodologies and flow for evolving needs.
• Plan and drive work for high-quality timely delivery.
• Provide technical guidance and conduct design reviews.

Skills

SystemVerilog

Verilog

IP design

Subsystem design

Microarchitecture

Digital design

AMBA AXI

Computer architecture

Scripting

Team collaboration

Education

Bachelor’s/Master’s/PhD in Electrical/Electronics/Computer Engineering

Tools

EDA tools

UPF

Synthesis

Timing analysis

Job description

Arm Limited in Cambridge is seeking a Staff Subsystem Design Engineer to lead RTL and subsystem IP design for next-generation compute platforms. You will specify, microarchitect and integrate complex IP and subsystems, collaborating with architecture, verification, and implementation teams to ensure high-quality, power-efficient designs.

The role requires 10+ years in RTL design, strong SystemVerilog/Verilog skills, and experience with AMBA AXI/APB interfaces, SVA and UVM are advantageous.