Senior SoC Subsystem Design Engineer

CamWebDir; United Kingdom; Hybrid; GBP 70,000 - 110,000; Full time

Job summary

Arm is seeking an experienced RTL design engineer to join the Front End design team within the Arm SE SoC Engineering group. You will contribute to specification, design and verification of subsystems and testchips, developing RTL and design intent deliverables while integrating IPs and ensuring timely delivery.

You will collaborate with verification and implementation teams to optimize designs, and you will plan work, track progress and report status to maintain quality and efficiency in a

Qualifications

• Hands-on SystemVerilog or Verilog HDL for RTL design.
• RTL design for complex SoC development.
• Experience in static design checks, power and clock domain crossing, synthesis.
• Experience with CPU, GPU, multimedia IP, interconnects and memory controllers in complex systems.
• Knowledge of UNIX environment and scripting (Python/Perl).
• Ability to write specifications and documentation describing complex designs.

Responsibilities

• Develop RTL and design intent deliverables (SDC, UPF) and integrate IPs.
• Collaborate with verification to review test plans and help debug design issues.
• Work with implementation teams to optimize designs for timing and area.
• Plan work, track progress, and report status to ensure high-quality delivery.

Skills

SystemVerilog

RTL design

Synthesis & CDC

CPU/GPU IP

Python/Perl

Documentation

Tools

UNIX scripting

Job description

Arm is seeking an experienced RTL design engineer to join the Front End design team within the Arm SE SoC Engineering group. You will contribute to specification, design and verification of subsystems and testchips, developing RTL and design intent deliverables while integrating IPs and ensuring timely delivery.

You will collaborate with verification and implementation teams to optimize designs, and you will plan work, track progress and report status to maintain quality and efficiency in a