Senior Design Engineer Bristol

AccelerComm Ltd; West of England; Hybrid; GBP 70,000 - 105,000; Full time

Benefits offered by this job

Bonus up to 20% of salary

EMI share options

Pension

Private health insurance

Flexible working hours

Hybrid working

Job summary

AccelerComm Ltd in Bristol is seeking Senior Design Engineers to work on space-qualified 5G base station technology for satellite deployment. You will deliver RTL designs for ASIC/FPGA, collaborate across architecture, verification, and implementation teams, and deploy on FPGA platforms.

The role involves working with the hardware department on cutting-edge non-terrestrial communications and offers hybrid working arrangements within Bristol, plus opportunities to contribute to EMI.

Qualifications

• Expert knowledge of RTL languages (Verilog/SystemVerilog) for complex ASIC/FPGA products.
• A strong skillset in delivering digital designs in the ASIC and FPGA industry.
• Optimization of timing and hardware resources for high-throughput data or signal processing.
• Track record in collaborating across teams to produce integrated solutions.
• Experience in technical documentation writing – design specifications and verification plans.
• Expert user of EDA tools for simulation and synthesis.
• Knowledge of communications signal processing algorithms (e.g., error correction).
• Familiarity with the AMBA bus protocols.
• Experience with C++/SystemC for design modelling and integration.
• Experience with high-speed interfaces such as PCIe or JESD.
• Python scripting knowledge.

Responsibilities

• Work closely with Algorithm and System Architecture teams to translate requirements into RTL micro-architectures.
• Implement designs targeting FPGA and ASIC using standard techniques with testbenches.
• Deploy designs onto FPGA development platforms for validation and integration.
• Engage with engineering methodology and propose efficiency/quality improvements.
• Collaborate across design flow: micro-architecture, design, verification, and physical implementation.

Skills

Verilog/SystemVerilog

ASIC/FPGA design

Timing/Resource optimization

Cross-functional collaboration

Documentation writing

EDA tool proficiency

Tools

EDA tools (simulation & synthesis)

PCIe/JESD high-speed interfaces

Job description

Senior Design Engineer

Department: Hardware

Employment Type: Full Time

Location: Bristol

Description

We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency.

You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions.

This is a Bristol based role; please also take a look at our vacancies in Southampton and Cambridge.

Key Responsibilities

• Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations
• Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
• Deploy your designs onto the latest FPGA development platforms for validation and system integration
• Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
• Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA

Skills, Knowledge & Expertise

Essential:

• Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
• A strong skillset in delivering digital designs in the ASIC and FPGA industry
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
• Track record in collaborating across teams to produce integrated solutions
• Experience in technical documentation writing – design specifications, user guides, verification plans
• Expert user of EDA tools for simulation and synthesis

Desirable:

• Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
• Familiarity with the AMBA bus protocols
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience using C++/SystemC for design modelling and integration
• Experience with high speed interfaces such as PCI-E or JESD
• Knowledge of a scripting language, such as Python
• Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
• Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools

Job Benefits

• We pay competitive salaries which depend on skills and experience.
• We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically. We offer a range of good quality company benefits including pension and private health insurance.
• We operate flexible working hours and offer hybrid working.