Senior Debug, Trace & Profiling Hardware Architect

SiFive Inc; Cambridge; On-site; GBP 80,000 - 110,000; Full time

Job summary

SiFive is seeking a hardware design engineer passionate about debug, trace and profiling IP to support the adoption of RISC-V for SOC designs. The engineer will lead enhancements and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC‑V International Association.

The focus is on debug, trace and profiling hardware, with challenges spanning configurable RTL generators, Chisel/FIRRTL integration, and verification.

Qualifications

• 7+ years of experience leading and contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware.
• MS or PhD in EE, CE, CS or related discipline.
• Knowledgeable in debug interfaces: JTAG and cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience with debugging tools and profiling methods.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
• Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.

Responsibilities

• Design the best debug, trace and profiling hardware for open RISC-V and TileLink architectures.
• Master designing hardware as configurable generators in a domain-specific language for elaborating digital logic.
• Architect, design and implement debug, trace and profiling hardware.
• Collaborate with architecture, performance, software and hardware teams for exploration and specification.
• Implement RTL generators for extensive configurability.
• Integrate design content into SiFive's Chisel/FIRRTL framework for automatic docs and tests.
• Perform sandbox verification and develop thorough verification test plans.
• Share knowledge via documentation and collaborative culture.

Skills

Team collaboration

Programming language concepts

Debugging & profiling tools

RTL hardware design

Chisel/Scala experience

RISC-V / CPU architecture knowledge

Git/Jira/Confluence familiarity

Education

MS or PhD in EE/CE/CS

Tools

Verilog

SystemVerilog

VHDL

Chisel/Scala

JTAG/cJTAG

Git/Jira/Confluence

Chisel/FIRRTL framework

Job description

SiFive is seeking a hardware design engineer passionate about debug, trace and profiling IP to support the adoption of RISC-V for SOC designs. The engineer will lead enhancements and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC‑V International Association.

The focus is on debug, trace and profiling hardware, with challenges spanning configurable RTL generators, Chisel/FIRRTL integration, and verification.