Senior RTL Design Engineer — High-Performance RISC-V Core

SiFive; Cambridge; On-site; GBP 152,000 - 186,000; Full time

Job summary

SiFive is seeking a CPU Microarchitecture/RTL design engineer to join a team delivering industry-leading CPU cores based on RISC-V. You will design features, ISA extensions, and integrate content within SiFive’s Chisel/FIRRTL framework, enabling automatic configuration and validation.

The role emphasizes high-performance hardware IP, collaboration across verification, physical design, and performance teams, with a focus on quality and efficient design workflows.

Qualifications

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 7+ years of design experience.
• Academic or professional experience with CPU RTL design in instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
• Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Strong software engineering skills including object-oriented, functional programming, templated metaprogramming, compiler infrastructures, data modeling, and test-driven development.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to framework improvements for automatic configuration and documentation.
• Perform initial sandbox verification and collaborate with the design verification team on test plans.
• Work with the physical implementation team to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for exploration and optimization to meet performance targets.
• Microarchitecture development and specification with emphasis on documentation and collaborative design.

Skills

CPU RTL design

Verilog/SystemVerilog/VHDL

Software engineering

Unit testing

Collaboration

Education

BS/MS in CS/CE/EE or related field

Tools

Chisel

FIRRTL

Git/GitHub

Confluence

Job description

SiFive is seeking a CPU Microarchitecture/RTL design engineer to join a team delivering industry-leading CPU cores based on RISC-V. You will design features, ISA extensions, and integrate content within SiFive’s Chisel/FIRRTL framework, enabling automatic configuration and validation.

The role emphasizes high-performance hardware IP, collaboration across verification, physical design, and performance teams, with a focus on quality and efficient design workflows.