Senior RTL Design Engineer — RISC-V Core Architect

SiFive; Cambridge; On-site; GBP 117,000 - 143,000; Full time

Job summary

SiFive is seeking a qualified engineer to architect, design, and implement features and ISA extensions in RISC-V CPU core generators using Chisel. You will integrate content into the FIRRTL framework and help automate documentation, verification tests, and packaged software.

You will verify designs with the verification team and work with physical implementation to optimize for frequency, area, and power. The role requires 3+ years of design experience, proficiency in Verilog/SystemVerilog/VHDL,

Qualifications

• BS/MS in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 3+ years of design experience.
• Academic or professional experience with CPU RTL design in instruction fetch, decode, branch prediction, coherent caches, cache prefetching, TLBs.
• Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Strong software engineering background including functional programming, templated metaprogramming, compiler infrastructures, data modeling, test-driven development.
• Attention to detail and teamwork-minded attitude.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements enabling automatic configuration/generation of docs, tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team on test plans.
• Work with the physical implementation team to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for exploration and optimization to meet performance targets.
• Microarchitecture development and documentation to promote knowledge sharing.

Skills

Design experience

Teamwork

Attention to detail

Software engineering

Education

BS/MS in CS/CE/EE or related field

Tools

Verilog

SystemVerilog

VHDL

Chisel

Scala

Bluespec

Jira

Confluence

Job description

SiFive is seeking a qualified engineer to architect, design, and implement features and ISA extensions in RISC-V CPU core generators using Chisel. You will integrate content into the FIRRTL framework and help automate documentation, verification tests, and packaged software.

You will verify designs with the verification team and work with physical implementation to optimize for frequency, area, and power. The role requires 3+ years of design experience, proficiency in Verilog/SystemVerilog/VHDL,