Debug/Trace/Profiling Design Engineer

SiFive Inc; Cambridge; On-site; GBP 80,000 - 110,000; Full time

Job summary

SiFive is seeking a hardware design engineer passionate about debug, trace and profiling IP to support the adoption of RISC-V for SOC designs. The engineer will lead enhancements and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC‑V International Association.

The focus is on debug, trace and profiling hardware, with challenges spanning configurable RTL generators, Chisel/FIRRTL integration, and verification.

Qualifications

• 7+ years of experience leading and contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware.
• MS or PhD in EE, CE, CS or related discipline.
• Knowledgeable in debug interfaces: JTAG and cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience with debugging tools and profiling methods.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
• Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.

Responsibilities

• Design the best debug, trace and profiling hardware for open RISC-V and TileLink architectures.
• Master designing hardware as configurable generators in a domain-specific language for elaborating digital logic.
• Architect, design and implement debug, trace and profiling hardware.
• Collaborate with architecture, performance, software and hardware teams for exploration and specification.
• Implement RTL generators for extensive configurability.
• Integrate design content into SiFive's Chisel/FIRRTL framework for automatic docs and tests.
• Perform sandbox verification and develop thorough verification test plans.
• Share knowledge via documentation and collaborative culture.

Skills

Team collaboration

Programming language concepts

Debugging & profiling tools

RTL hardware design

Chisel/Scala experience

RISC-V / CPU architecture knowledge

Git/Jira/Confluence familiarity

Education

MS or PhD in EE/CE/CS

Tools

Verilog

SystemVerilog

VHDL

Chisel/Scala

JTAG/cJTAG

Git/Jira/Confluence

Chisel/FIRRTL framework

Job description

SiFive is seeking a hardware design engineer passionate about designing industry-leading debug, trace and profiling IP to support the widespread adoption of RISC-V as the architecture of choice for SOC designs. The engineer will lead enhancements of existing debug/trace/profiling hardware and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC-V International Association., The focus of this position is on debug, trace, and profiling hardware. The successful applicant will address the following challenges:

• Design the best debug, trace and profiling hardware for open RISC-V and TileLink architectures.
• Master designing hardware as configurable generators in a domain-specific software language for elaborating digital logic.
• Work in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance., Architect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators so elements self-configure to achieve extensive configurability as a first-class consideration.
• Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Ensure knowledge is shared via creation and maintenance of great documentation and participation in a collaborative design culture.
  Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG and cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience with debugging tools and profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object-oriented and/or functional programming language.
• Knowledge of Chisel/Scala, RISC-V architecture, Git/Jira/Confluence is a plus.
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors.
• MS or PhD in EE, CE, CS or a related technical discipline.