RISC-V CPU RTL Architect & Microarchitecture Engineer

SiFive; Cambridge; On-site; GBP 60,000 - 90,000; Full time

Job summary

SiFive in Cambridge, United Kingdom, is seeking a CPU Microarchitecture/RTL design engineer to help build industry-leading RISC‑V cores. You will design features, implement ISA extensions, and advance Chisel-based workflows across the development stack.

You will verify designs, collaborate with verification, physical design, and performance teams, and contribute to documentation and reusable test content in a fast-paced, collaborative environment.

Qualifications

• BS/MS in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 3+ years of design experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Strong software engineering background including functional programming templated metaprogramming and DSL work.
• Attention to detail and teamwork.

Responsibilities

• Architect, design and implement features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into Chisel/FIRRTL framework and contribute improvements to enable automatic configuration/generation of docs, tests, and packaged software.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
• Microarchitecture development and specification; document knowledge and promote collaborative design.

Skills

Teamwork

Attention to detail

Test-driven development

Adaptive unit tests

Communication

Education

BS/MS in CS/CE/EE or equivalent

Tools

Verilog

SystemVerilog

VHDL

Chisel

FIRRTL

Scala/Chisel

Job description

SiFive in Cambridge, United Kingdom, is seeking a CPU Microarchitecture/RTL design engineer to help build industry-leading RISC‑V cores. You will design features, implement ISA extensions, and advance Chisel-based workflows across the development stack.

You will verify designs, collaborate with verification, physical design, and performance teams, and contribute to documentation and reusable test content in a fast-paced, collaborative environment.