RISC-V Debug, Trace & Profiling IP Architect

SiFive; Cambridge; On-site; GBP 60,000 - 90,000; Full time

Job summary

SiFive is seeking a hardware design engineer in Cambridge with a passion for developing advanced debug, trace, and profiling hardware. This role involves collaborating with cross-functional teams to design high-performance hardware that supports RISC-V architecture.

The ideal candidate will have over 7 years of experience in RTL design, strong proficiency in Verilog or VHDL, and a Master's or PhD in a related field. SiFive promotes diversity and an inclusive work environment.

Qualifications

• 7+ years of industry experience in architecture and RTL design.
• Proficient in Verilog, System Verilog, or VHDL hardware design.
• Ability to work well with others in a team-oriented environment.

Responsibilities

• Architect, design, and implement debug and profiling hardware.
• Work with various teams in architecture/microarchitecture exploration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework.

Skills

Debug, trace and profiling architecture

Hardware (RTL) design in Verilog

Collaboration and team work

Experience with debugging tools

Knowledge of Chisel/Scala

Education

MS or PhD in EE, CE, CS or a related technical discipline

Tools

Git

Jira

Confluence

Job description

SiFive is seeking a hardware design engineer in Cambridge with a passion for developing advanced debug, trace, and profiling hardware. This role involves collaborating with cross-functional teams to design high-performance hardware that supports RISC-V architecture.

The ideal candidate will have over 7 years of experience in RTL design, strong proficiency in Verilog or VHDL, and a Master's or PhD in a related field. SiFive promotes diversity and an inclusive work environment.