Staff RTL Design Engineer - CPU Midcore

SiFive; Cambridge; On-site; GBP 75,000 - 115,000; Full time

Job summary

SiFive is hiring a CPU Microarchitecture/RTL design engineer to join a team delivering industry‑leading CPU cores based on the open‑source RISC‑V architecture. You will design features, extend ISA, and integrate content into Chisel/FIRRTL while coordinating with verification and physical teams.

You will contribute to documentation, improve testbenches, and drive performance exploration to meet aggressive goals in a fast‑paced environment.

Qualifications

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 5+ years of design experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills/background, including object‑oriented, aspect‑oriented, and particularly functional programming.
• Templated metaprogramming, in any language.
• Compiler infrastructures, particularly for domain‑specific languages.
• Data modeling, particularly intermediate representations for optimizing or transforming compiler passes.
• Test‑driven development, particularly ability to write adaptive unit tests.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and share the belief that engineering is teamwork.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
• Microarchitecture development and specification.
• Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Skills

CPU RTL design

Software engineering

Test-driven development

Teamwork

Attention to detail

Functional programming

Templated metaprogramming

Education

BS/MS in CS/CE/EE or related field

Tools

Verilog/SystemVerilog

VHDL

Scala/Chisel

Git/Github

UVM

Job description

Job Description

As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. The role involves bringing new hardware IP to market quickly, with high quality and exceptional performance in a fast‑paced dynamic environment.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
• Microarchitecture development and specification.
• Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 5+ years of design experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Strong software engineering skills/background, including object‑oriented, aspect‑oriented, and particularly functional programming.
• Templated metaprogramming, in any language.
• Compiler infrastructures, particularly for domain‑specific languages.
• Data modeling, particularly intermediate representations for optimizing or transforming compiler passes.
• Test‑driven development, particularly ability to write adaptive unit tests.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and share the belief that engineering is teamwork.

Nice‑to‑Haves

• Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
• Knowledge of RISC‑V architecture.
• Expertise in CPU processor designs in one or more of the following areas: instruction decode; register renaming, reorder buffer, and instruction scheduling; vector units; load‑store unit.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/Github, Jira, Confluence.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export‑control laws, or, if you are not already authorized, obtaining any necessary export license(s) or other approvals.

SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.