Lead Debug/Trace/Profiling Design Engineer

SiFive; Cambridge; On-site; GBP 70,000 - 95,000; Full time

Job summary

SiFive is seeking a Hardware Design Technical Lead to architect and implement innovative debug, trace, and profiling hardware. This role is pivotal to accelerate the adoption of RISC-V architecture in SOC designs across diverse applications.

Qualified candidates will have deep knowledge in debug architectures and work collaboratively with cross-functional teams. This position offers the opportunity to contribute significantly to SiFive's cutting-edge processor core designs in an agile environment.

Qualifications

• Knowledgeable in debug, trace, and profiling architecture.
• Familiarity with debug interfaces, JTAG, and cJTAG.
• Understanding of CPU architectures and SoC design.

Responsibilities

• Architect, design, and implement debug, trace, and profiling hardware.
• Collaborate with various teams for design specification.
• Integrate new design content into SiFive's frameworks.
• Conduct initial sandbox verification with the design verification team.
• Create and maintain comprehensive documentation.

Skills

Debug architecture knowledge

Profiling techniques

JTAG interfaces

CPU architectures

Job description

SiFive is seeking a hardware design technical lead who is passionate about designing industry‑leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating a highly customizable line of processor cores with fast time‑to‑market by designing the hardware as highly configurable generators. Leveraging technology and ideas from the software industry, this role will enable hardware design with the speed and agility of software development, supporting our entire IP portfolio – Essential, Intelligence, Performance, and Automotive product lines.

Job Responsibilities

• Architect, design, and implement debug, trace, and profiling hardware.
• Work with architecture, performance, software, and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators so that elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to framework improvements to enable automatic configuration/generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
• Ensure knowledge is shared via creation and maintenance of comprehensive documentation, fostering a culture of collaborative design.

Position Requirements

• Knowledgeable in debug, trace, and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG, and cJTAG.
• Knowledgeable in CPU architectures, power management, and SoC design.