Senior RISC-V RTL Design Engineer (Microarchitecture)

SiFive; Cambridge; On-site; GBP 75,000 - 115,000; Full time

Job summary

SiFive is hiring a CPU Microarchitecture/RTL design engineer to join a team delivering industry‑leading CPU cores based on the open‑source RISC‑V architecture. You will design features, extend ISA, and integrate content into Chisel/FIRRTL while coordinating with verification and physical teams.

You will contribute to documentation, improve testbenches, and drive performance exploration to meet aggressive goals in a fast‑paced environment.

Qualifications

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 5+ years of design experience.
• Academic or professional experience with CPU RTL design.
• Proficiency in hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills/background, including object‑oriented, aspect‑oriented, and particularly functional programming.
• Templated metaprogramming, in any language.
• Compiler infrastructures, particularly for domain‑specific languages.
• Data modeling, particularly intermediate representations for optimizing or transforming compiler passes.
• Test‑driven development, particularly ability to write adaptive unit tests.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and share the belief that engineering is teamwork.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
• Microarchitecture development and specification.
• Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Skills

CPU RTL design

Software engineering

Test-driven development

Teamwork

Attention to detail

Functional programming

Templated metaprogramming

Education

BS/MS in CS/CE/EE or related field

Tools

Verilog/SystemVerilog

VHDL

Scala/Chisel

Git/Github

UVM

Job description

SiFive is hiring a CPU Microarchitecture/RTL design engineer to join a team delivering industry‑leading CPU cores based on the open‑source RISC‑V architecture. You will design features, extend ISA, and integrate content into Chisel/FIRRTL while coordinating with verification and physical teams.

You will contribute to documentation, improve testbenches, and drive performance exploration to meet aggressive goals in a fast‑paced environment.