Hardware Verification Engineer

Baya Systems; Remote; GBP 70,000 - 90,000; Full time

Job summary

A leading technology firm is seeking a Senior Hardware Verification Engineer to design and implement test plans for complex IPs. You will collaborate with cross-functional teams, write UVM/SystemVerilog code, and ensure coverage is met. The ideal candidate must have extensive experience in verification and excellent problem-solving skills. Remote work is available within the United Kingdom, providing flexibility while contributing to innovative technology solutions.

Qualifications

• 8+ years of hands-on experience in block-level/IP-level/SOC-level verification.
• Familiarity with industry-standard EDA tools for simulation and debug.
• Knowledge of ARM AMBA protocols such as AXI, APB, and AHB.

Responsibilities

• Collaborate with design and architecture teams to create test plans.
• Write UVM/SystemVerilog code to implement the test plan.
• Work with design and DV engineers to debug failures.

Skills

Verilog

SystemVerilog

UVM-based testbenches

Python

Problem-solving

Communication skills

Education

BS/MS in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools

Job description

Job Title:

Senior Hardware Verification Engineer

Location:

England, United Kingdom (Remote anywhere inside the country)

About the Role:

We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

• Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
• Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification
• Proficiency in Verilog, SystemVerilog
• Familiarity with industry-standard EDA tools for simulation and debug
• Deep experience with UVM-based testbenches
• Experience with modern programming languages like Python
• Knowledge of ARM AMBA protocols such as AXI, APB, and AHB
• Understanding of ARM CHI protocol is a plus
• Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs
• Experience with formal verification techniques, emulation platforms is a plus
• Excellent problem-solving skills and attention to detail
• Strong communication and collaboration skills

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