Senior Digital ASIC/SoC Design Engineer – Onsite

TechNET IT Recruitment Ltd; Provence-Alpes-Côte d'Azur; On-site; EUR 70,000 - 80,000; Full time

Benefits offered by this job

Annual bonus up to 10%

Job summary

Meyreuil, France-based Senior Digital IC / ASIC Design Engineer role requiring hands-on HDL design, RTL verification, and SoC integration. You will contribute to architecture, verification, and silicon validation within a secure R&D environment.

Key skills include Verilog/SystemVerilog/VHDL, RTL simulation, and experience with Synopsys/Cadence tools. Onsite role with strong collaboration across engineering teams and opportunities to influence future chips.

Qualifications

• Experience in digital IC/ASIC development.
• Proficient in HDL languages (Verilog/SystemVerilog/VHDL).
• Strong RTL verification and timing analysis skills.

Responsibilities

• RTL design and development of complex digital logic.
• Integration and verification of digital IP and SoC components.
• Product feasibility studies and architecture definition.
• Development of verification environments and test methodologies.
• Design analysis, debugging and validation activities.
• Close collaboration with cross-functional engineering teams.
• Driving continuous improvements to design and verification methodologies.

Skills

Digital ASIC/SoC design

Verilog/SystemVerilog/VHDL

RTL simulation & verification

Synopsys/Cadence tools

Static Timing Analysis

Python/TCL scripting

Embedded microcontrollers

Tools

Synopsys

Cadence

RTL design tools

Job description

Meyreuil, France-based Senior Digital IC / ASIC Design Engineer role requiring hands-on HDL design, RTL verification, and SoC integration. You will contribute to architecture, verification, and silicon validation within a secure R&D environment.

Key skills include Verilog/SystemVerilog/VHDL, RTL simulation, and experience with Synopsys/Cadence tools. Onsite role with strong collaboration across engineering teams and opportunities to influence future chips.