Senior EDA Software Engineer – SoC/FPGA, Hybrid

IC Resources; Île-de-France; Hybrid; EUR 48,000 - 70,000; Full time

Benefits offered by this job

International engineering environment

Exposure to AI tools (Cursor/Claude)

Career development

Job summary

IC Resources is seeking a Senior Software Engineer for hybrid work in Paris / Montigny-le-Bretonneux / Sophia Antipolis. The role combines software development in C++/Python with hardware awareness of Verilog/VHDL and FPGA/ASIC concepts, within an Agile/Kanban environment.

The successful candidate will develop tools to parse memory maps, generate HDL code, run unit tests, and support CI/CD pipelines while collaborating across software, hardware, and verification teams.

Qualifications

• Bachelor's, Master's or PhD in Computer Science, Electrical Engineering or a related discipline.
• Strong OO programming skills in C++, Python, or Java.
• Experience with HDL (Verilog/VHDL) and FPGA/ASIC concepts.

Responsibilities

• Develop and enhance C++ and Python software used to parse SoC memory map specifications and generate HDL code and technical documentation.
• Write unit tests and troubleshoot issues across software, tooling and CI/CD environments.
• Support validation and verification teams with regression analysis and debugging.
• Optimise software performance, scalability and usability for large-scale SoC design environments.
• Produce and maintain documentation for software modules and features.
• Collaborate with architects, software engineers and verification teams to deliver robust technical solutions.
• Work within Agile and Kanban development environments using Jira and Confluence.

Skills

Object-oriented programming

English proficiency

Education

Bachelor's/Master's/PhD in CS or EE

Tools

C++

Python

Java

Verilog

VHDL

CI/CD pipelines

Jira

Confluence

Cursor AI

Claude Code

Job description

IC Resources is seeking a Senior Software Engineer for hybrid work in Paris / Montigny-le-Bretonneux / Sophia Antipolis. The role combines software development in C++/Python with hardware awareness of Verilog/VHDL and FPGA/ASIC concepts, within an Agile/Kanban environment.

The successful candidate will develop tools to parse memory maps, generate HDL code, run unit tests, and support CI/CD pipelines while collaborating across software, hardware, and verification teams.