Senior Digital Verification Engineer – ASIC/SoC Expert

NXP Semiconductors; Grenoble; Hybrid; EUR 85,000 - 110,000; Full time

Job summary

NXP Semiconductors is seeking a Senior HW Digital Design Verification Engineer in Grenoble to lead verification strategy for complex ASICs/SoCs. You will build testbenches, implement UVM-based flows, and collaborate with design and software teams to ensure robust designs.

You will develop coverage-driven verification plans, perform formal checks when applicable, and mentor junior engineers while advancing verification methodologies within the team.

Qualifications

• 5+ years of digital design verification experience on complex ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM.
• Experience building verification environments and test plans from scratch.
• Solid understanding of digital design principles, architectures, and protocols.
• Experience with industry-standard EDA verification tools; scripting in Python/Perl/Tcl.
• Familiarity with formal verification is a plus.
• Excellent problem-solving and communication skills.

Responsibilities

• Develop and execute verification plans for complex digital blocks/sub-systems.
• Implement UVM-based testbenches and coverage-driven verification flows.
• Create and maintain verification environments using SystemVerilog, UVM, and other tools.
• Develop directed, constrained-random, and assertion-based testbenches to validate design functionality.
• Perform functional and code coverage analysis to ensure verification completeness.
• Debug complex design/verification issues and collaborate with design teams.

Skills

SystemVerilog

UVM

Testbench development

Debugging

Python scripting

Formal verification

Communication

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Simulation tools

Waveform viewers

Coverage analysis tools

Job description

NXP Semiconductors is seeking a Senior HW Digital Design Verification Engineer in Grenoble to lead verification strategy for complex ASICs/SoCs. You will build testbenches, implement UVM-based flows, and collaborate with design and software teams to ensure robust designs.

You will develop coverage-driven verification plans, perform formal checks when applicable, and mentor junior engineers while advancing verification methodologies within the team.