MTS Verification Engineer: PCIe & PHY Integration

Rambus; Marseille; Hybride; EUR 70 000 - 90 000; Plein temps

Avantages offerts par ce poste

Competitive compensation package

Flexible work environment

Employee benefits

Résumé du poste

A premier silicon technology firm is seeking a mid-level Design and Verification Engineer. The role involves Verilog RTL design and verification for PCIe Controller development. Candidates should have 6+ years of experience in verification, strong analytical skills, and a Bachelor's or Master's degree in a relevant field. The position allows for hybrid work arrangements, requiring office attendance three days a week in Sofia, Bulgaria. Competitive salary and benefits are offered.

Qualifications

• 6+ years experience with verification using Verilog and SystemVerilog.
• Strong experience in ASIC/VLSI verification.
• Ability to work in international teams.

Responsabilités

• Verilog RTL design for IP integration.
• Development and support of various verification environments.
• Maintain verification productivity metrics.

Connaissances

Verilog verification

Strong analytical skills

Excellent interpersonal skills

Problem-solving skills

Experience in multinational companies

Formation

Bachelor or Master's degree in Electronics Engineering

Outils

Verilog

SystemVerilog

FPGA prototyping

UVM

Python

Shell scripting

Description du poste

A premier silicon technology firm is seeking a mid-level Design and Verification Engineer. The role involves Verilog RTL design and verification for PCIe Controller development. Candidates should have 6+ years of experience in verification, strong analytical skills, and a Bachelor's or Master's degree in a relevant field. The position allows for hybrid work arrangements, requiring office attendance three days a week in Sofia, Bulgaria. Competitive salary and benefits are offered.