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Rambus in Sofia, Bulgaria, is seeking a mid-level Design and Verification Engineer to join our PHY integration team. You will contribute to pre-silicon RTL design and verification for PCIe Controller Soft IP and PHY integrations in a global environment.
The role requires strong Verilog/SystemVerilog experience, ASIC/VLSI verification, and collaboration with international teams. Travel flexibility and excellent English are expected as we support customers worldwide.
Rambus in Sofia, Bulgaria, is seeking a mid-level Design and Verification Engineer to join our PHY integration team. You will contribute to pre-silicon RTL design and verification for PCIe Controller Soft IP and PHY integrations in a global environment.
The role requires strong Verilog/SystemVerilog experience, ASIC/VLSI verification, and collaboration with international teams. Travel flexibility and excellent English are expected as we support customers worldwide.