MTS Verification Engineering

Rambus

Marseille

Hybrid

EUR 70,000 - 90,000

Full time

14 days+

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Benefits offered by this job

Competitive compensation package
Flexible work environment
Employee benefits

Job summary

A premier silicon technology firm is seeking a mid-level Design and Verification Engineer. The role involves Verilog RTL design and verification for PCIe Controller development. Candidates should have 6+ years of experience in verification, strong analytical skills, and a Bachelor's or Master's degree in a relevant field. The position allows for hybrid work arrangements, requiring office attendance three days a week in Sofia, Bulgaria. Competitive salary and benefits are offered.

Qualifications

  • 6+ years experience with verification using Verilog and SystemVerilog.
  • Strong experience in ASIC/VLSI verification.
  • Ability to work in international teams.

Responsibilities

  • Verilog RTL design for IP integration.
  • Development and support of various verification environments.
  • Maintain verification productivity metrics.

Skills

Verilog verification
Strong analytical skills
Excellent interpersonal skills
Problem-solving skills
Experience in multinational companies

Education

Bachelor or Master's degree in Electronics Engineering

Tools

Verilog
SystemVerilog
FPGA prototyping
UVM
Python
Shell scripting

Job description

Overview

Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team in Sofia, Bulgaria. The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe Controller Soft IP development and PHYs integrations, on leading-edge PCI-Express and CXL controller technologies. This is a Full Time position.

Overview

Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team in Sofia, Bulgaria. The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe Controller Soft IP development and PHYs integrations, on leading-edge PCI-Express and CXL controller technologies. This is a Full Time position.

Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work if you are located in Sofia.

Responsibilities

  • Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module
  • Verifying the IP integration with dedicated simulation environment
  • Development and support test cases of different verification environments
  • Support worldwide customers on the IP integration
  • Get familiar to existing verification process, propose improvements
  • Maintain the traceability from the customer specification or the product specification to the architecture and verification results.
  • Track and maintain verification productivity metrics
  • Reporting periodically on progress and difficulties

Qualifications

  • "Can Do" Attitude
  • Bachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplines
  • Strong analytical and problem-solving skills
  • Excellent interpersonal skills
  • Open for traveling abroad
  • Work in international organization and specially with teams in France, USA, Taiwan and India
  • Because Rambus operates internationally, very good English is important for the position

Your Technical Experience

  • 6+ years experience verification with Verilog, SystemVerilog, FPGA prototyping
  • 6+ years experience with complex ASIC/VLSI verification
  • 6+ years experience with Avery or UVM. Any 3rd party VIP experience is a plus.
  • 6+ years experience in multinational company
  • Experience with creating documentation, python, shell & etc.

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work .

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .

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