Senior RTL & UVM Verification Engineer, eFPGA IP

Menta SAS; Valbonne; Sur place; EUR 45 000 - 70 000; Plein temps

Résumé du poste

A technology company in the French Riviera is seeking a Senior Hardware & Verification Engineer to lead verification flows for complex hardware IP. You will support project delivery and integration, contributing to high-impact hardware development. The ideal candidate has solid experience in RTL design and UVM-based verification, proficient in Verilog/SystemVerilog/VHDL, and has strong scripting skills. Join a collaborative R&D team focused on innovation and responsible progress.

Qualifications

• Solid experience in RTL design and UVM-based verification.
• Proficiency in Verilog/SystemVerilog/VHDL required.
• Familiarity with EDA tools like Questa, VCS, or Xcelium.
• Strong scripting skills in Python/TCL, Unix environment, and Git.

Responsabilités

• Lead and manage verification flows for complex hardware IP.
• Support project delivery and IP product integration.

Connaissances

RTL design

UVM-based verification

Verilog / SystemVerilog / VHDL

EDA tools (Questa, VCS, Xcelium)

SoC IPs (Ethernet, USB, DDR)

Scripting (Python, TCL)

Unix environment

Git

Fluent English

French

Formation

Master’s degree or equivalent

Description du poste

A technology company in the French Riviera is seeking a Senior Hardware & Verification Engineer to lead verification flows for complex hardware IP. You will support project delivery and integration, contributing to high-impact hardware development. The ideal candidate has solid experience in RTL design and UVM-based verification, proficient in Verilog/SystemVerilog/VHDL, and has strong scripting skills. Join a collaborative R&D team focused on innovation and responsible progress.