Digital Verification Engineer — PCIe/RISC-V/UVM Expert

Arago Inc.; Paris; On-site; EUR 90,000 - 150,000; Full time

Benefits offered by this job

Relocation assistance

Healthcare coverage

Pension contributions

Professional development

Stock options

25 days PTO

Transport subsidy 50%

Job summary

Arago Inc. in Paris is seeking a highly skilled verification engineer to ensure the functional integrity, performance, and reliability of next-generation optical chips.

You will develop robust verification plans, collaborate with architects, designers, and customers, and implement UVM-based environments using SystemVerilog. English proficiency required; French a plus.

This role offers relocation support, meaningful stock options, and a fast-paced startup culture.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• Proven SystemVerilog verification expertise.
• Experience with UVM and modern verification environments.
• Knowledge of AXI/AXIStream, APB/AHB, I2C, JTAG, PCIe; Verifying high-speed interfaces.
• Experience verifying RISC-V CPU cores in an ASIC context.
• Strong analytical and communication skills; customer-driven projects; interdisciplinary teamwork.
• English proficiency; French is a plus.

Responsibilities

• Develop robust verification plans for complex digital and mixed-signal optical chip designs.
• Collaborate with architects, designers, and customers to translate logic requirements into verification strategies.
• Perform netlist-level simulations with SDF back-annotation for timing-accurate verification.
• Support FPGA/ASIC bring-up and post-silicon validation as needed.
• Develop, maintain, and optimize testbenches and verification components using SystemVerilog features.
• Design scalable UVM environments for block- and system-level verification; enable regression automation.
• Verify PCIe endpoints and root complex devices; use protocol analyzers for validation.
• Contribute to verification of RISC-V cores; develop test plans and coverage.
• Plan end-to-end ASIC verification from block to full-chip integration; participate in design reviews.

Skills

SystemVerilog for verification

UVM verification environments

PCIe protocol verification

RISC-V verification

Digital verification

Customer communication

English proficiency

French language (plus)

Education

Bachelor/Master/PhD in Electrical or Computer Engineering

Tools

SDF back-annotation

UVM-based testbenches

Formal verification tools

Protocol analyzers

Formal verification suites

Job description

Arago Inc. in Paris is seeking a highly skilled verification engineer to ensure the functional integrity, performance, and reliability of next-generation optical chips.

You will develop robust verification plans, collaborate with architects, designers, and customers, and implement UVM-based environments using SystemVerilog. English proficiency required; French a plus.

This role offers relocation support, meaningful stock options, and a fast-paced startup culture.